Abstract: An oscillator circuit includes a first integrator unit to charge a first capacitor at a first integration node, a second integrator unit to charge a second capacitor at a second integration node, a chopped comparator unit and a logic unit. The chopped comparator unit includes a switching unit, a sensing comparator and a replica comparator. The switching unit is configured to couple the first integration node, the second integration node and a reference voltage VREF to the sensing comparator and the replica comparator, depending upon a phase determined by a first input clock signal C1 and a second input clock signal C2, which have opposite phases. The logic unit is configured to generate signals C1, C2, D1, D2, E1, E2 for controlling each integrator unit.

Abstract: An oscillator circuit arrangement includes a switched capacitor circuit at least one capacitor selectively coupled to one of a supply terminal and a terminal for ground potential. A chopper circuit is disposed between the switched capacitor circuit and a comparator. The chopper circuit selectively couples one of input terminals and a reference potential terminal to its output terminals. A buffer circuit is coupled to the output of the comparator circuit. The buffer circuit is connected to the switched capacitor circuit and to the chopper circuit to control selective coupling operations therein.

Abstract: An oscillator circuit arrangement includes a switched capacitor circuit at least one capacitor selectively coupled to one of a supply terminal and a terminal for ground potential. A chopper circuit is disposed between the switched capacitor circuit and a comparator. The chopper circuit selectively couples one of input terminals and a reference potential terminal to its output terminals. A buffer circuit is coupled to the output of the comparator circuit. The buffer circuit is connected to the switched capacitor circuit and to the chopper circuit to control selective coupling operations therein.

Abstract: An oscillator circuit includes a first integrator unit to charge a first capacitor at a first integration node, a second integrator unit to charge a second capacitor at a second integration node, a chopped comparator unit and a logic unit. The chopped comparator unit includes comprises a switching unit, a sensing comparator and a replica comparator. The switching unit is configured to couple the first integration node, the second integration node and a reference voltage VREF to the sensing comparator and the replica comparator, depending upon a phase determined by a first input clock signal C1 and a second input clock signal C2, which have opposite phases. The logic unit is configured to generate signals C1, C2, D1, D2, E1, E2 for controlling each integrator unit.

Abstract: The oscillator circuit comprises first and second integrator units with a first capacitor charged at a first integration node and a second capacitor charged at a second integration node. A comparator unit is arranged between a first switching unit, which is connected to the integration nodes and to a reference signal (VREF), and a second switching unit. The comparator unit compares a signal from the first or second integration node with the reference signal. The second switching unit is connected to a logic unit configured to provide signals controlling the first integrator unit, the second integrator unit, the first switching unit and the second switching unit, so that a periodic operation is generated by alternatingly activating the first integrator unit and the second integrator unit.

Abstract: In an embodiment an oscillator circuit comprises a first integrator-comparator unit, a second integrator-comparator unit, and a logic circuit. The first integrator-comparator unit is prepared to provide a first signal as a function of a first integration of a first charging current and a subsequent comparison of a first integration signal resulting from the first integration with a reference signal. The second integrator-comparator unit is prepared to provide a third signal as a function of a second integration of a second charging current and a subsequent comparison of a second integration signal resulting from the second integration with the reference signal. The logic circuit is adapted to provide a clock signal, a first and a second measurement signal for respectively controlling the first and the second integrator-comparator unit.

Abstract: The oscillator circuit comprises first and second integrator units with a first capacitor charged at a first integration node and a second capacitor charged at a second integration node. A comparator unit is arranged between a first switching unit, which is connected to the integration nodes and to a reference signal (VREF), and a second switching unit. The comparator unit compares a signal from the first or second integration node with the reference signal. The second switching unit is connected to a logic unit configured to provide signals controlling the first integrator unit, the second integrator unit, the first switching unit and the second switching unit, so that a periodic operation is generated by alternatingly activating the first integrator unit and the second integrator unit.

Abstract: In an embodiment an oscillator circuit comprises a first integrator-comparator unit, a second integrator-comparator unit, and a logic circuit. The first integrator-comparator unit is prepared to provide a first signal as a function of a first integration of a first charging current and a subsequent comparison of a first integration signal resulting from the first integration with a reference signal. The second integrator-comparator unit is prepared to provide a third signal as a function of a second integration of a second charging current and a subsequent comparison of a second integration signal resulting from the second integration with the reference signal. The logic circuit is adapted to provide a clock signal, a first and a second measurement signal for respectively controlling the first and the second integrator-comparator unit.

Abstract: A device for de-palletizing stacks of blanks stacked on pallets with flat spacing layers disposed in-between, includes a displaceable gripping head and an insertion tool arranged approximately horizontally oriented on the gripping head. The insertion tool is positioned in front of at least one stack of blanks through displacement of the gripping head for being inserted with an approximately horizontal movement between the stack of blanks and the spacing layer for picking up the stack of blanks and for removing the picked up stack of blanks from the spacing layer through a displacement of the gripping head. At least one lifting mechanism is coupled to the gripping head for lifting up one side of the stack of blanks.