Patents by Inventor Josip Popovic

Josip Popovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250004516
    Abstract: An apparatus and method for efficiently managing voltage droop among replicated compute circuits of an integrated circuit. In various implementations, an integrated circuit includes multiple, replicated compute circuits, each with the circuitry of multiple lanes of execution. Control circuitry of the integrated circuit identifies, early in execution pipelines, groups of instructions to be executed by a corresponding compute circuit, and generates a total power consumption estimate for the groups. The control circuitry maintains N previous total power consumption estimates, and stores the N power consumption estimates in staging circuitry referred to as an “instruction history pipeline.” If any differences between total power consumption estimates of different stages of the instruction history pipeline exceeds a corresponding threshold, then the control circuitry reduces, late in the execution pipeline, the rate of instruction execution of computation lanes of a corresponding compute circuit.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Josip Popovic, Anshuman Mittal, Kellie Marks
  • Publication number: 20240393861
    Abstract: An apparatus and method for efficiently managing voltage transients on a power rail caused by current transients of an integrated circuit. In various implementations, a computing system includes a processing circuit that executes instructions of a compiler that includes a current transients mitigator. When executing the instructions of the current transients mitigator, the processing circuit generates an estimate of a time rate of current flow being drawn from or returned to the power rail based on instruction types of a first sequence of instructions. Based on the estimate exceeds a threshold, the processing circuit replaces the first sequence of instructions with a second sequence of instructions that provides a smaller estimate. The second sequence is issued to the one or more compute circuits that utilize the power rail, rather than the first sequence.
    Type: Application
    Filed: December 14, 2023
    Publication date: November 28, 2024
    Inventors: Josip Popovic, Rashad Oreifej, Robert Alan Marc Gottlieb
  • Publication number: 20240320034
    Abstract: An apparatus and method for efficiently managing voltage droop among replicated compute circuits of an integrated circuit. In various implementations, an integrated circuit includes multiple, replicated compute circuits, each including circuitry to process tasks grouped into a work block. When a scheduling window has begun, the scheduler determines a value for a threshold number of idle compute circuits that can be simultaneously activated based on one or more of a number of active compute circuits, an operating clock frequency, a measured operating temperature, a number of pending work blocks, and an application identifier. If the scheduler determines that there is a count of idle compute circuits that is equal to or greater than the threshold number of idle compute circuits, then the scheduler limits the number of idle compute circuits that can be activated at one time to the threshold number.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Inventors: Josip Popovic, Anshuman Mittal
  • Publication number: 20240085970
    Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes first partition and a second partition. The second partition includes video pre-processing circuitry that identifies regions of a video frame to be presented on a screen or monitor that don't change or regions that can have one or more of resolution and color accuracy be below a threshold. The first partition includes a parallel data processor with one or more compute units, each with multiple lanes of execution. Based on the identified regions, the first partition generates an execution mask indicating which lanes of the compute units are inactive. The parallel data processor copies result data from the active lanes to outputs of the inactive lanes.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Josip Popovic, Anshuman Mittal