Patents by Inventor Jothilingam RAMALINGAM

Jothilingam RAMALINGAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210062325
    Abstract: A method of depositing a backside film layer on a backside of a substrate includes loading a substrate having one or more films deposited on a front side of the substrate onto a substrate support of a processing chamber, depositing, from the sputter target, a target material on the backside of the substrate to form a backside layer on the backside of the substrate, and applying an RF bias to an electrode disposed within the substrate support while depositing the target material. The front side of the substrate faces the substrate support and is spaced from a top surface of the substrate support, and a backside of the substrate faces a sputter target of the processing chamber.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 4, 2021
    Inventors: Jothilingam RAMALINGAM, Xiaozhou CHE, Yong CAO, Shane LAVAN, Chunming ZHOU
  • Publication number: 20210050195
    Abstract: Methods and apparatus for reducing burn-in time of a physical vapor deposition shield, including: sputtering a dielectric target having a first dielectric constant to form a dielectric layer upon an inner surface of a shield, wherein the shield includes an aluminum oxide coating having a second dielectric constant in an amount sufficient to reduce the burn-in time, and wherein the first dielectric constant and second dielectric constant are substantially similar.
    Type: Application
    Filed: August 16, 2020
    Publication date: February 18, 2021
    Inventors: Jothilingam RAMALINGAM, William FRUCHTERMAN
  • Publication number: 20210033974
    Abstract: Embodiments of the present disclosure generally relate to a multilayer stack used as a mask in extreme ultraviolet (EUV) lithography and methods for forming a multilayer stack. In one embodiment, the method includes forming a carbon layer over a film stack, forming a metal rich oxide layer on the carbon layer by a physical vapor deposition (PVD) process, forming a metal oxide photoresist layer on the metal rich oxide layer, and patterning the metal oxide photoresist layer. The metal oxide photoresist layer is different from the metal rich oxide layer and is formed by a process different from the PVD process. The metal rich oxide layer formed by the PVD process improves adhesion of the metal oxide photoresist layer and increases the secondary electrons during EUV lithography, which leads to decreased EUV dose energies.
    Type: Application
    Filed: June 2, 2020
    Publication date: February 4, 2021
    Inventors: Tejinder SINGH, Lifan YAN, Abhijit B. MALLICK, Daniel Lee DIEHL, Ho-yung HWANG, Jothilingam RAMALINGAM
  • Publication number: 20200350160
    Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for backside stress engineering of substrates to combat film stresses and bowing issues. In one embodiment, a method of depositing a film layer on a backside of a substrate is provided. The method includes flipping a substrate at a factory interface so that the backside of the substrate is facing up, and transferring the flipped substrate from the factory interface to a physical vapor deposition chamber to deposit a film layer on the backside of the substrate. In another embodiment, an apparatus for depositing a backside film layer on a backside of a substrate, which includes a substrate supporting surface configured to support the substrate at or near the periphery of the substrate supporting surface without contacting an active region on a front side of the substrate.
    Type: Application
    Filed: April 13, 2020
    Publication date: November 5, 2020
    Inventors: Chunming ZHOU, Jothilingam RAMALINGAM, Yong CAO, Kevin Vincent MORAES, Shane LAVAN
  • Publication number: 20200273705
    Abstract: Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 27, 2020
    Inventors: Tejinder SINGH, Suketu Arun PARIKH, Daniel Lee DIEHL, Michael Anthony STOLFI, Jothilingam RAMALINGAM, Yong CAO, Lifan YAN, Chi-I LANG, Hoyung David HWANG
  • Patent number: 10734235
    Abstract: Systems and methods for sputtering a layer of refractory metal layer onto a barrier layer disposed on a substrate are disclosed herein. In one or more embodiments, a method of sputter depositing a tungsten structure in an integrated circuit includes: moving a substrate into a plasma processing chamber and onto a substrate support in opposition to a sputter target assembly comprising a tungsten target having no more than ten parts per million of carbon and no more than ten parts per million of oxygen present as impurities; flowing krypton into the plasma processing chamber; and exciting the krypton into a plasma to deposit, by sputtering, a tungsten film layer on a material layer of a substrate supported by the substrate support. In some embodiments, the target assembly further includes a titanium backing plate and an aluminum bonding layer disposed between the titanium backing plate and the tungsten target.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 4, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jothilingam Ramalingam, Thanh X. Nguyen, Zhiyong Wang, Jianxin Lei, Xianmin Tang
  • Publication number: 20200090957
    Abstract: Methods and apparatus for processing substrates are provided herein. In some embodiments, a shroud for controlling gas flow in a process chamber includes a closed walled body having an upper end and a lower end, the closed walled body defining a first opening of the shroud at the lower end and a second opening of the shroud at the upper end, wherein the second opening is offset from the first opening; and a top wall disposed atop a portion of the upper end of the closed walled body in a position above the first opening to define, together with a remaining portion of the upper end of the closed walled body, the second opening, wherein the shroud is configured to divert a gas flow from the second opening through the first opening.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 19, 2020
    Inventors: Jothilingam Ramalingam, Kirankumar Neelasandra Savandaiah, Fuhong Zhang, William Johanson
  • Publication number: 20200048760
    Abstract: Methods of forming a film layer using a HiPIMS PVD process include providing a bias to a substrate in a processing region of a process chamber, the substrate comprising a surface feature and the processing region of the process chamber comprising a sputter target, delivering at least one energy pulse to the sputter target to create a sputtering plasma of a sputter gas in the processing region, the at least one energy pulse having an average voltage between about 600 volts and about 1500 volts and an average current between about 50 amps and about 1000 amps at a frequency which is less than 5 kHz and greater than 100 Hz, and directing the sputtering plasma toward the sputter target to form an ionized species comprising material sputtered from the sputter target, the ionized species forming a film in the feature of the substrate having improved bottom coverage.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 13, 2020
    Inventors: KISHOR KALATHIPARAMBIL, ADOLPH M ALLEN, JIANXIN LEI, JOTHILINGAM RAMALINGAM, VIACHSLAV BABAYAN
  • Patent number: 10388532
    Abstract: Ruthenium containing gate stacks and methods of forming ruthenium containing gate stacks are described. The ruthenium containing gate stack comprises a polysilicon layer on a substrate; a silicide layer on the polysilicon layer; a barrier layer on the silicide layer; a ruthenium layer on the barrier layer; and a spacer layer comprising a nitride on sides of the ruthenium layer, wherein the ruthenium layer comprises substantially no ruthenium nitride after formation of the spacer layer. Forming the ruthenium layer comprises sputtering the ruthenium in a krypton environment on a high current electrostatic chuck comprising a high resistivity ceramic material. The sputtered ruthenium layer is annealed at a temperature greater than or equal to about 500° C.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 20, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jothilingam Ramalingam, Ross Marshall, Jianxin Lei, Xianmin Tang
  • Publication number: 20180337052
    Abstract: Systems and methods for sputtering a layer of refractory metal layer onto a barrier layer disposed on a substrate are disclosed herein. In one or more embodiments, a method of sputter depositing a tungsten structure includes: moving a substrate into a plasma processing chamber and onto a substrate support in opposition to a sputter target assembly comprising a tungsten target having no more than ten parts per million of carbon and no more than ten parts per million of oxygen present as impurities; and generating a plasma within the plasma processing chamber to deposit, by sputtering, a tungsten film layer on a material layer of a substrate supported by the substrate support. In some embodiments, the target assembly further includes a titanium backing plate and an aluminum bonding layer disposed between the titanium backing plate and the tungsten target.
    Type: Application
    Filed: August 1, 2018
    Publication date: November 22, 2018
    Inventors: Jothilingam RAMALINGAM, Thanh X. NGUYEN, Zhiyong WANG, Jianxin LEI, Xianmin TANG
  • Patent number: 10043670
    Abstract: Systems and methods for sputtering a layer of refractory metal layer onto a barrier layer disposed on a substrate are disclosed herein. In one or more embodiments, a method of sputter depositing a tungsten structure in an integrated circuit includes: moving a substrate into a plasma processing chamber and onto a substrate support in opposition to a sputter target assembly comprising a tungsten target having no more than ten parts per million of carbon and no more than ten parts per million of oxygen present as impurities; flowing krypton into the plasma processing chamber; and exciting the krypton into a plasma to deposit, by sputtering, a tungsten film layer on a material layer of a substrate supported by the substrate support. In some embodiments, the target assembly further includes a titanium backing plate and an aluminum bonding layer disposed between the titanium backing plate and the tungsten target.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 7, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jothilingam Ramalingam, Thanh X. Nguyen, Zhiyong Wang, Jianxin Lei, Xianmin Tang
  • Publication number: 20180096852
    Abstract: Ruthenium containing gate stacks and methods of forming ruthenium containing gate stacks are described. The ruthenium containing gate stack comprises a polysilicon layer on a substrate; a silicide layer on the polysilicon layer; a barrier layer on the silicide layer; a ruthenium layer on the barrier layer; and a spacer layer comprising a nitride on sides of the ruthenium layer, wherein the ruthenium layer comprises substantially no ruthenium nitride after formation of the spacer layer. Forming the ruthenium layer comprises sputtering the ruthenium in a krypton environment on a high current electrostatic chuck comprising a high resistivity ceramic material. The sputtered ruthenium layer is annealed at a temperature greater than or equal to about 500° C.
    Type: Application
    Filed: September 28, 2017
    Publication date: April 5, 2018
    Inventors: Jothilingam Ramalingam, Ross Marshall, Jianxin Lei, Xianmin Tang
  • Publication number: 20170117153
    Abstract: Systems and methods for sputtering a layer of refractory metal layer onto a barrier layer disposed on a substrate are disclosed herein. In one or more embodiments, a method of sputter depositing a tungsten structure in an integrated circuit includes: moving a substrate into a plasma processing chamber and onto a substrate support in opposition to a sputter target assembly comprising a tungsten target having no more than ten parts per million of carbon and no more than ten parts per million of oxygen present as impurities; flowing krypton into the plasma processing chamber; and exciting the krypton into a plasma to deposit, by sputtering, a tungsten film layer on a material layer of a substrate supported by the substrate support. In some embodiments, the target assembly further includes a titanium backing plate and an aluminum bonding layer disposed between the titanium backing plate and the tungsten target.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 27, 2017
    Inventors: Jothilingam RAMALINGAM, Thanh X. NGUYEN, Zhiyong WANG, Jianxin LEI, Xianmin TANG
  • Patent number: 9461137
    Abstract: Embodiments of the present disclosure include tungsten silicide nitride films and methods for depositing tungsten silicide nitride films. In some embodiments, a thin film microelectronic device includes a semiconductor substrate having a tungsten gate electrode stack comprising a tungsten silicide nitride film having a formula WxSiyNz, wherein x is about 19 to about 22 atomic percent, y is about 57 to about 61 atomic percent, and z is about 15 to about 20 atomic percent. In some embodiments, a method of processing a substrate disposed in physical vapor deposition (PVD) chamber, includes: exposing a substrate having a gate insulating layer to a plasma formed from a first process gas comprising nitrogen and argon; sputtering silicon and tungsten material from a target disposed within a processing volume of the PVD chamber; depositing atop the gate insulating layer a tungsten silicide nitride layer as described above; and depositing a bulk tungsten layer atop the tungsten silicide nitride layer.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 4, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jothilingam Ramalingam, Rajkumar Jakkaraju, Jianxin Lei, Zhiyong Wang
  • Publication number: 20160168687
    Abstract: Methods and apparatus for reducing particles generated in a process carried out in a process chamber are provided herein. In some embodiments, a method of reducing particles generated by a process of depositing a refractory metal on a substrate in a process chamber includes: forming a coating atop an inner surface of the process chamber prior to carrying out the process, wherein the coating has a thermal expansion coefficient that is within 20% of a thermal expansion coefficient of the refractory metal deposited during the process. In some embodiments, a process chamber configured for depositing a refractory metal on a substrate includes: a coating disposed atop an inner surface of the process chamber and having a thermal expansion coefficient that is within 20% of a thermal expansion coefficient of the refractory metal.
    Type: Application
    Filed: February 12, 2015
    Publication date: June 16, 2016
    Inventors: JOTHILINGAM RAMALINGAM, JIANXIN LEI
  • Publication number: 20150118833
    Abstract: A method of depositing a contact layer material includes sputtering a target including a metal and a dopant. The contact layer material is conductive and may be used in a transistor device to connect a conductive region, such as a source region or a drain region of metal-oxide semiconductor field effect transistor, to a contact plug. The contact plug is used to connect the source/drain region formed in a semiconducting substrate to metal wiring layers formed above the gate level of a semiconductor device. The resulting contact layer may be a metal silicide including the dopant. In some embodiments, the sputtered metal may be nickel and the dopant may be phosphorous and the resulting contact layer a nickel silicide doped with phosphorous. Embodiments described, in general, can provide reduced contact resistance and thus improved performance in semiconductor devices.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Inventors: Jianxin LEI, Jothilingam RAMALINGAM, Chi-Nung NI