Patents by Inventor Jotiba Koparde

Jotiba Koparde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250094071
    Abstract: Methods, systems, and devices for techniques for data transfer operations are described. A memory system may select a source set of memory cells and a destination set of memory cells using one or more counters corresponding to access operations for the source and the destination. For example, as part of a data transfer operation, the memory system may prioritize transferring data from a block with a lower quantity of read operations to a block with a lower quantity of access operations. In some cases, the memory system may prioritize transferring data from a page with a lower quantity of read operations to a page with a slower read duration.
    Type: Application
    Filed: September 27, 2024
    Publication date: March 20, 2025
    Inventor: Jotiba Koparde
  • Publication number: 20250013391
    Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.
    Type: Application
    Filed: July 15, 2024
    Publication date: January 9, 2025
    Inventors: Nitul Gohain, Jameer Mulani, Jotiba Koparde
  • Patent number: 12124723
    Abstract: Methods, systems, and devices for techniques for data transfer operations are described. A memory system may select a source set of memory cells and a destination set of memory cells using one or more counters corresponding to access operations for the source and the destination. For example, as part of a data transfer operation, the memory system may prioritize transferring data from a block with a lower quantity of read operations to a block with a lower quantity of access operations. In some cases, the memory system may prioritize transferring data from a page with a lower quantity of read operations to a page with a slower read duration.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: October 22, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Jotiba Koparde
  • Publication number: 20240281346
    Abstract: Methods, systems, and devices for programming failure handling during data folding are described. A memory system may support a non-blocking exception handling process for handling program failures that occur during folding. For example, if a program failure occurs at a given page, the memory system may mark the failed page as storing uncorrectable data (e.g., associated with an uncorrectable error correction code (UECC) error) rather than as being associated with the program failure. Based on the marking, the memory system may continue the folding operation, allowing the data to be moved to another page of a physical destination block. After the folding operation is complete, the memory system may replace a failed physical destination block that includes the failed page with a spare block and retire the failed physical destination block.
    Type: Application
    Filed: February 6, 2024
    Publication date: August 22, 2024
    Inventors: Jotiba Koparde, Nicola Colella, Sridhar Prudviraj Gunda
  • Patent number: 12061819
    Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: August 13, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Nitul Gohain, Jameer Mulani, Jotiba Koparde
  • Publication number: 20230342060
    Abstract: Methods, systems, and devices for techniques for data transfer operations are described. A memory system may select a source set of memory cells and a destination set of memory cells using one or more counters corresponding to access operations for the source and the destination. For example, as part of a data transfer operation, the memory system may prioritize transferring data from a block with a lower quantity of read operations to a block with a lower quantity of access operations. In some cases, the memory system may prioritize transferring data from a page with a lower quantity of read operations to a page with a slower read duration.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Inventor: Jotiba Koparde
  • Publication number: 20230176778
    Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Nitul Gohain, Jameer Mulani, Jotiba Koparde