Abstract: A circuit for inverting the latter half of an expected signal representative of an output expected for a device to be tested with regard to operation thereof by a tester comprises a first flip-flop having a D-input terminal supplied with an inverting signal for controlling inversion of an expected pattern, a R-input terminal supplied with a reference clock signal for determining the period of the expected pattern and a C-input terminal supplied with a clock signal synchronized with transitions in an output pattern of a device to be tested as to whether it operates as desired or not, an exclusive-OR circuit having inputs supplied with the output of the first flip-flop and the expected pattern, respectively, an OR circuit having inputs supplied with the reference clock signal and the clock signal, respectively, and a second flip-flop having a D-input terminal supplied with the output of the exclusive-OR circuit and a C-input terminal supplied with the output of the OR circuit.