Patents by Inventor Joung Cheul Choi
Joung Cheul Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929362Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, an active well, an emitter, a base, a collector, a body contact region, and a blocking well. The semiconductor substrate may have a first conductive type. The active well may be formed in the semiconductor substrate. The active well may have a second conductive type. The emitter and the base may be formed in the active well. The collector may be formed in the semiconductor substrate outside the active well. The body contact region may be formed in the semiconductor substrate to electrically connect the collector with the semiconductor substrate. The body contact region may have a conductive type substantially the same as that of the collector. The blocking well may be configured to surround an outer wall of the body contact region. The blocking well may have the second conductive type.Type: GrantFiled: November 23, 2021Date of Patent: March 12, 2024Assignee: SK hynix Inc.Inventors: Joung Cheul Choi, Jae Young You
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Patent number: 11916063Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.Type: GrantFiled: August 9, 2021Date of Patent: February 27, 2024Assignee: SK hynix Inc.Inventors: Joung Cheul Choi, Chang Seok Song
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Patent number: 11742343Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.Type: GrantFiled: August 9, 2021Date of Patent: August 29, 2023Assignee: SK hynix Inc.Inventors: Joung Cheul Choi, Chang Seok Song
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Publication number: 20220085008Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, an active well, an emitter, a base, a collector, a body contact region, and a blocking well. The semiconductor substrate may have a first conductive type. The active well may be formed in the semiconductor substrate. The active well may have a second conductive type. The emitter and the base may be formed in the active well. The collector may be formed in the semiconductor substrate outside the active well. The body contact region may be formed in the semiconductor substrate to electrically connect the collector with the semiconductor substrate. The body contact region may have a conductive type substantially the same as that of the collector. The blocking well may be configured to surround an outer wall of the body contact region. The blocking well may have the second conductive type.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Applicant: SK hynix Inc.Inventors: Joung Cheul CHOI, Jae Young YOU
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Patent number: 11201145Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, an active well, an emitter, a base, a collector, a body contact region, and a blocking well. The semiconductor substrate may have a first conductive type. The active well may be formed in the semiconductor substrate. The active well may have a second conductive type. The emitter and the base may be formed in the active well. The collector may be formed in the semiconductor substrate outside the active well. The body contact region may be formed in the semiconductor substrate to electrically connect the collector with the semiconductor substrate. The body contact region may have a conductive type substantially the same as that of the collector. The blocking well may be configured to surround an outer wall of the body contact region. The blocking well may have the second conductive type.Type: GrantFiled: December 21, 2018Date of Patent: December 14, 2021Assignee: SK hynix Inc.Inventors: Joung Cheul Choi, Jae Young You
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Publication number: 20210366897Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Joung Cheul CHOI, Chang Seok SONG
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Publication number: 20210366898Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Joung Cheul CHOI, Chang Seok SONG
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Patent number: 11088133Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.Type: GrantFiled: August 29, 2019Date of Patent: August 10, 2021Assignee: SK hynix Inc.Inventors: Joung Cheul Choi, Chang Seok Song
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Publication number: 20200273856Abstract: A semiconductor integrated circuit may include a first power line, a second power line, a third power line and a protection circuit. The first power line may receive an external voltage. The second power line may receive a voltage greater than the external voltage. The third power line may receive a voltage less than the external voltage applied to the first power line and the voltage applied to the second power line. The protection circuit may from a current path between the first power line, the second power line and the third power line when a surge voltage may be applied to the first power line to discharge the surge voltage to the third power line.Type: ApplicationFiled: November 5, 2019Publication date: August 27, 2020Applicant: SK hynix Inc.Inventors: Chang Hwi LEE, Jung Eon MOON, Hyeng Ouk LEE, Joung Cheul CHOI
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Publication number: 20200194424Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.Type: ApplicationFiled: August 29, 2019Publication date: June 18, 2020Inventors: Joung Cheul CHOI, Chang Seok SONG
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Publication number: 20190378833Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, an active well, an emitter, a base, a collector, a body contact region, and a blocking well. The semiconductor substrate may have a first conductive type. The active well may be formed in the semiconductor substrate. The active well may have a second conductive type. The emitter and the base may be formed in the active well. The collector may be formed in the semiconductor substrate outside the active well. The body contact region may be formed in the semiconductor substrate to electrically connect the collector with the semiconductor substrate. The body contact region may have a conductive type substantially the same as that of the collector. The blocking well may be configured to surround an outer wall of the body contact region. The blocking well may have the second conductive type.Type: ApplicationFiled: December 21, 2018Publication date: December 12, 2019Applicant: SK hynix Inc.Inventors: Joung Cheul CHOI, Jae Young YOU
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Publication number: 20170338219Abstract: A semiconductor integrated circuit device having a first clamping circuit, a second clamping circuit, a third clamping circuit, a first path-changing line and a second path-changing line. The first clamping circuit may be connected between an input/output pad and a power pad. The first clamping circuit may include a plurality of diodes serially connected with each other. The second clamping circuit may be connected between the input/output pad and a ground pad. The second clamping circuit may include a plurality of diodes serially connected with each other. The third clamping circuit may be connected between the power pad and the ground pad. The third clamping circuit may include a plurality of diodes serially connected with each other. First and second path-changing lines may be configured to direct static electricity paths.Type: ApplicationFiled: November 29, 2016Publication date: November 23, 2017Inventors: Joung Cheul CHOI, Jin Woo KIM
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Publication number: 20130335123Abstract: Provided is a driver IC chip of a liquid crystal display (LCD). The driver IC chip has a layout of power pads, which may uniformly apply an adhesive force on the entire adhesion surface of the driver IC chip, when the driver IC chip is mounted on a display panel according to a chip-on-glass (COG) technique.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Silicon Works Co., Ltd.Inventors: Joung Cheul CHOI, An Young Kim, Joon Ho NA, Dae Seong Kim, Dae-Keun Han
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Patent number: 8541888Abstract: A pad layout structure of a driver IC chip to be mounted to a liquid crystal display panel. The pad layout structure includes power pad sections placed at respective four corners of the driver IC chip and each having a first power pad for supplying first power to the driver IC chip, a second power pad for supplying second power to the driver IC chip, a third power pad for supplying third power to the driver IC chip and a fourth power pad for supplying fourth power to the driver IC chip.Type: GrantFiled: May 22, 2009Date of Patent: September 24, 2013Assignee: Silicon Works Co., Ltd.Inventors: Joung Cheul Choi, An Young Kim, Joon Ho Na, Dae Seong Kim, Dae Keun Han
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Patent number: 8279617Abstract: A pad layout structure of a driver IC chip of a liquid crystal display device includes dummy power pads and dummy ground pads, which are disposed in corners of the driver IC chip and are connected to main power pads and main ground pads by metal lines in a chip-on-film (COF) package. Accordingly, it is possible to reduce the resistance of power supply lines and ground lines, to minimize a power dip of a block located far away from the main power pads and main ground pads, and to prevent a failure in power application, which may occur due to a decrease of adhesive strength at a specific position, by dispersing the adhesion positions of the power pads and ground pads.Type: GrantFiled: September 16, 2010Date of Patent: October 2, 2012Assignee: Silicon Works Co., Ltd.Inventors: Joung Cheul Choi, Joon Ho Na, Dae Seong Kim
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Publication number: 20110169813Abstract: A display panel driving circuit includes N number of amplifiers configured to supply N number of output voltages to a display panel; N number of output switches configured to transmit output signals from the N number of amplifiers through N number of pads to the display panel; and a plurality of charge sharing switches configured to share charges among the N number of pads, wherein the charge sharing switches are formed in the pads.Type: ApplicationFiled: January 6, 2011Publication date: July 14, 2011Applicant: SILICON WORKS CO., LTDInventors: Byung-Yun Jin, Jong-Geun Park, Hyun-Ho Cho, Joung-Cheul Choi, Joon-Ho Na
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Publication number: 20110089576Abstract: A pad layout structure of a driver IC chip to be mounted to a liquid crystal display panel. The pad layout structure includes power pad sections placed at respective four corners of the driver IC chip and each having a first power pad for supplying first power to the driver IC chip, a second power pad for supplying second power to the driver IC chip, a third power pad for supplying third power to the driver IC chip and a fourth power pad for supplying fourth power to the driver IC chip.Type: ApplicationFiled: May 22, 2009Publication date: April 21, 2011Applicant: SILICON WORKS CO., LTD.Inventors: Joung Cheul CHOI, An Young Kim, Joon Ho Na, Dae Seong Kim, Dae Keun Han
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Publication number: 20110075390Abstract: A pad layout structure of a driver IC chip of a liquid crystal display device includes dummy power pads and dummy ground pads, which are disposed in corners of the driver IC chip and are connected to main power pads and main ground pads by metal lines in a chip-on-film (COF) package. Accordingly, it is possible to reduce the resistance of power supply lines and ground lines, to minimize a power dip of a block located far away from the main power pads and main ground pads, and to prevent a failure in power application, which may occur due to a decrease of adhesive strength at a specific position, by dispersing the adhesion positions of the power pads and ground pads.Type: ApplicationFiled: September 16, 2010Publication date: March 31, 2011Applicant: SILICON WORKS CO., LTDInventors: Joung Cheul CHOI, Joon Ho NA, Dae Seong KIM