Patents by Inventor Joung Park
Joung Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240117211Abstract: A paint composition is prepared by mixing each of an acrylic resin, an acrylic polyol resin, a polycarbonate diol resin, a diisocyanate, a solvent, and an antibacterial agent in appropriate amounts. As a result, the paint composition has improved physical properties and effective antibacterial activities.Type: ApplicationFiled: April 28, 2023Publication date: April 11, 2024Inventors: Hyun Jung Kim, Ho Tak Jeon, Jae Sik Seo, Ji Hwan Park, Dae Joung Cho
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Patent number: 11935980Abstract: A filtering panel includes a molding layer part; a pattern layer part having an incident surface through which light emitted from a light source and viewing light transmitted to an observer enter, and an accommodation surface which is the reverse surface of the incident surface, wherein the molding layer part is stacked on the incident surface so as to be adjacent thereto, and the pattern layer part adjusts the optical paths of the emitted light and the viewing light; and a filtering layer part formed on a lower incident surface of the pattern layer part having the incident surface of the viewing light that enters from a lower region below a horizontal reference line, wherein the reflectivity of the visible light in the viewing light incident on the lower region is made greater than that of an upper region above the reference line by means of mirror reflection.Type: GrantFiled: November 27, 2019Date of Patent: March 19, 2024Assignees: POSCO CO., LTD, RESEARCH INSTITUTE OF INDUSTRIAL SCIENCE & TECHNOLOGYInventors: Sung-Ju Tark, Kun-Hoon Baek, Jun-Hong Kim, Youn-Joung Choi, Ji-Sang Park
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Patent number: 11911430Abstract: The present invention relates to a food composition for relieving stress, and specifically, to a food composition for relieving stress, which reduces secretion of the stress hormone cortisol and increases secretion of the happy hormone serotonin by containing fermented and aged noni and calamansi as active ingredients, has no side effects, and is safe for the human body. The composition of the present invention may be used as a health functional food or a pharmaceutical composition. The composition of the present invention has an excellent anti-stress effect.Type: GrantFiled: December 29, 2021Date of Patent: February 27, 2024Assignees: ATOMY OROT CO., LTD., NSTBIO CO., LTD.Inventors: Im Joung La, Geum Su Seong, Eun Young Park, Yong Deok Kim, Eun Min Kim, Soo Jin Kim
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Memory device having improved program and erase operations and operating method of the memory device
Patent number: 11880582Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.Type: GrantFiled: February 11, 2021Date of Patent: January 23, 2024Assignee: SK hynix Inc.Inventors: Byung In Lee, Hee Joung Park, Keon Soo Shim, Sang Heon Lee, Jae Il Tak -
Patent number: 11114163Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.Type: GrantFiled: June 3, 2020Date of Patent: September 7, 2021Assignee: SK hynix Inc.Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin
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MEMORY DEVICE HAVING IMPROVED PROGRAM AND ERASE OPERATIONS AND OPERATING METHOD OF THE MEMORY DEVICE
Publication number: 20210165603Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.Type: ApplicationFiled: February 11, 2021Publication date: June 3, 2021Applicant: SK hynix Inc.Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK -
Memory device having improved program and erase operations and operating method of the memory device
Patent number: 10950306Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.Type: GrantFiled: July 12, 2019Date of Patent: March 16, 2021Assignee: SK hynix Inc.Inventors: Byung In Lee, Hee Joung Park, Keon Soo Shim, Sang Heon Lee, Jae Il Tak -
Publication number: 20200294596Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.Type: ApplicationFiled: June 3, 2020Publication date: September 17, 2020Applicant: SK hynix Inc.Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN
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Publication number: 20200294597Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.Type: ApplicationFiled: June 3, 2020Publication date: September 17, 2020Applicant: SK hynix Inc.Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN
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Patent number: 10706929Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.Type: GrantFiled: March 23, 2018Date of Patent: July 7, 2020Assignee: SK hynix Inc.Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin
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MEMORY DEVICE HAVING IMPROVED PROGRAM AND ERASE OPERATIONS AND OPERATING METHOD OF THE MEMORY DEVICE
Publication number: 20200211650Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.Type: ApplicationFiled: July 12, 2019Publication date: July 2, 2020Applicant: SK hynix Inc.Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK -
Patent number: 10304544Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.Type: GrantFiled: December 8, 2017Date of Patent: May 28, 2019Assignee: SK hynix Inc.Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin, Dong Hyuk Chae
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Publication number: 20190043584Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.Type: ApplicationFiled: March 23, 2018Publication date: February 7, 2019Applicant: SK hynix Inc.Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN
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Publication number: 20180322929Abstract: A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.Type: ApplicationFiled: December 8, 2017Publication date: November 8, 2018Inventors: Hee Joung PARK, Kyeong Seung KANG, Won Chul SHIN, Dong Hyuk CHAE
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Patent number: 9965388Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.Type: GrantFiled: January 4, 2017Date of Patent: May 8, 2018Assignee: SK Hynix Inc.Inventors: Ki Chang Chun, Hee Joung Park, Tae Seung Shin, Sung Lae Oh
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Publication number: 20170337130Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.Type: ApplicationFiled: January 4, 2017Publication date: November 23, 2017Inventors: Ki Chang CHUN, Hee Joung PARK, Tae Seung SHIN, Sung Lae OH
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Patent number: 8648965Abstract: An image signal processor and a method for processing an image signal thereof are disclosed. When the image signal processor executes an automatic chroma gain control (ACC), the image signal processor adjusts a variable rate of ACC gain according to a size of an input color signal to reduce a time for processing the ACC. Even if a difference between the size of the input color signal and the size of a reference color signal is large, the ACC is rapidly processed. As a result, transient phenomenon disappears from a screen.Type: GrantFiled: January 17, 2008Date of Patent: February 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Hye-joung Park
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Patent number: 8274607Abstract: An image processing apparatus is provided, including: a first image processing unit which converts an input image signal into a brightness signal and a chromaticity signal; and a second image processing unit which adjusts a bandwidth used to filter the chromaticity signal to correspond to a noise level of the image signal, and filters the chromaticity signal with the adjusted bandwidth to extract a chrominance signal.Type: GrantFiled: July 30, 2009Date of Patent: September 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Hye-joung Park
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Patent number: D962256Type: GrantFiled: November 5, 2020Date of Patent: August 30, 2022Assignee: The Procter & Gamble CompanyInventors: Naoki Miyamoto, Lin Yu, Youn Joung Park, Yasuharu Shirai
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Patent number: D982595Type: GrantFiled: July 18, 2022Date of Patent: April 4, 2023Assignee: The Procter & Gamble CompanyInventors: Naoki Miyamoto, Lin Yu, Youn Joung Park, Yasuharu Shirai