Abstract: The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.

Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to form a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: The present disclosure describes an exemplary method that forms spacer stacks with metallic compound layers. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

Abstract: The present disclosure describes a method for forming a silicon-based, carbon-rich, low-k ILD layer with a carbon concentration between about 15 atomic % and about 20 atomic %. For example, the method includes depositing a dielectric layer, over a substrate, with a dielectric material having a dielectric constant below 3.9 and a carbon atomic concentration between about 15% and about 20%; exposing the dielectric layer to a thermal process configured to outgas the dielectric material; etching the dielectric layer to form openings; and filling the openings with a conductive material to form conductive structures.

Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to from a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.

Abstract: An exemplary method that forms spacer stacks with metallic compound layers is disclosed. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

Abstract: The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.

Abstract: The present disclosure describes a method for forming a silicon-based, carbon-rich, low-k ILD layer with a carbon concentration between about 15 atomic % and about 20 atomic %. For example, the method includes depositing a dielectric layer, over a substrate, with a dielectric material having a dielectric constant below 3.9 and a carbon atomic concentration between about 15% and about 20%; exposing the dielectric layer to a thermal process configured to outgas the dielectric material; etching the dielectric layer to form openings; and filling the openings with a conductive material to form conductive structures.

Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

Abstract: The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to an interlayer dielectric (ILD) layer in a semiconductor device. In one example, the ILD layer is over a substrate and includes a dielectric with a dielectric constant of less than about 3.3 and a hardness of at least about 3 GPa. The semiconductor device also includes an interconnect formed in the ILD layer.

Abstract: A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH3 bonds less than the first content of Si—CH3 bonds.

Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to from a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.

Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to form a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite 0-atoms and O2 gas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where O2 gas may be used and, along with the O2 gas, precursors containing embedded Si—O—Si bonds, such as (CH3O)3—Si—O—Si—(CH3O)3) and (CH3)3—Si—O—Si—(CH3)3 may be used.

Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes depositing a hard mask. A multi-layer structure is deposited over the hard mark. The multi-layer structure includes a bottom layer, a first middle layer over the bottom layer, a second middle layer over the first middle layer, and a top layer over the second middle layer. The first middle layer comprises a SiCxHyOz material in which the SiCxHyOz material has a silicon-to-silicon bond content in a range from about 0.5% to about 5%. The multi-layer structure is patterned to form a patterned first middle layer having openings. The hard mask is etched through the openings in the patterned first middle layer.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.