Abstract: Integrated circuit devices are provided including a pair of differential I/O lines and a driver circuit. The driver circuit is configured to drive the pair of differential I/O lines responsive to a write command signal. First and second precharge circuits are also provided. The first precharge circuit is configured to precharge the pair of differential I/O lines to a first voltage during a first mode of operation responsive to an active command signal. The second precharge circuit is configured to precharge the pair of differential I/O lines to a second voltage, lower than the first voltage, during a second mode of operation responsive to the active command signal. Related methods of operating integrated circuit devices are also provided.

Abstract: A memory device includes a data line and a variable delay precharge circuit that receives a column bank address signal and a write enable signal and that precharges the data line responsive to the column bank address signal at a time that is determined by a state of the write enable signal. For example, the variable delay precharge circuit may include a precharge circuit operative to precharge the data line responsive to a precharge control signal, and a variable delay precharge control signal generator circuit that receives the column bank address signal and the write enable signal and that delays the precharge control signal with respect to the column bank address signal responsive to the write enable signal.

Abstract: A buffer circuit may include an output terminal, a pull-up transistor, a pull-down transistor, and first and second logic gates. The pull-up transistor is connected between the output terminal and a supply voltage, and the pull-up transistor pulls the output terminal up to the supply voltage responsive to a pull-up control signal. The pull-down transistor is connected between the output terminal and a reference voltage, and the pull-down transistor pulls the output terminal down to the reference voltage responsive to a pull-down control signal. The first logic gate may generate the pull-up control signal at a first output node responsive to a control signal and a data signal, and the first logic gate may include a plurality of serially connected transistors in an electrical path between the supply voltage and the first output node.

Abstract: The present invention provides a current sense amplifier including first and second sense transistors having cross-coupled gates and drains. The current sense amplifier further includes first and second load devices having first terminals connected to respective drains of the first and second sense transistors and a latch having first and second inputs connected to respective drains of the first and second sense transistors. The amplifier still further includes an enable device that is responsive to an enable signal and has a first terminal connected to second terminals of the first and second load devices and a first output of the latch.

Abstract: The present invention provides a current sense amplifier including first and second sense transistors having cross-coupled gates and drains. The current sense amplifier further includes first and second load devices having first terminals connected to respective drains of the first and second sense transistors and a latch having first and second inputs connected to respective drains of the first and second sense transistors. The amplifier still further includes an enable device that is responsive to an enable signal and has a first terminal connected to second terminals of the first and second load devices and a first output of the latch.