Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: A composition for a semiconductor encapsulant includes an epoxy resin, a curing agent, a filler, and a polyrotaxane, wherein the polyrotaxane includes a linear polymer A, an end group B, and a cyclic molecule C threaded through by the linear polymer. The cyclic molecule C has at least one functional group selected from the group consisting of an epoxy group, an oxetane group, and an alkoxysilyl group, or has a functional group capable of reacting with the at least one functional group.

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: The present invention relates to a conductive two-dimensional polyaniline (PANT) nanosheets template. The method comprises polymerizing aniline on an ice surface. The PANI nanosheets show distinctly high current flows of 5.5 mA at 1 V and a high electrical conductivity of 35 S/cm, which mark a significant improvement over previous values on other PANIs reported over the past decades. These improved electrical properties of the PANI nanosheets are attributed to the long-range ordered edge-on ?-stacking of the quinoid ring, ascribed to the ice surface-assisted vertical growth of PANI. The PANI nanosheet can be easily transferred onto various types of substrates via float-off from the ice surfaces. In addition, PANI can be patterned into any shape using predetermined masks, and this is expected to facilitate the eventual convenient and inexpensive application of conducting polymers in versatile electronic device forms.

Abstract: The present invention relates to a new method of synthesizing two-dimensional polyaniline (PANI) nanosheets using ice as a removable hard template. The method comprises polymerizing aniline on an ice surface. The synthesized PANI nanosheets show distinctly high current flows of 5.5 mA at 1 V and a high electrical conductivity of 35 S/cm, which mark a significant improvement over previous values on other PANIs reported over the past decades. These improved electrical properties of the PANI nanosheets are attributed to the long-range ordered edge-on n-stacking of the quinoid ring, ascribed to the ice surface-assisted vertical growth of PANI. The PANI nanosheet can be easily transferred onto various types of substrates via float-off from the ice surfaces. In addition, PANI can be patterned into any shape using predetermined masks, and this is expected to facilitate the eventual convenient and inexpensive application of conducting polymers in versatile electronic device forms.

Abstract: The present invention relates to a new method of synthesizing two-dimensional polyaniline (PANI) nanosheets using ice as a removable hard template. The method comprises polymerizing aniline on an ice surface. The synthesized PANI nanosheets show distinctly high current flows of 5.5 mA at 1 V and a high electrical conductivity of 35 S/cm, which mark a significant improvement over previous values on other PANIs reported over the past decades. These improved electrical properties of the PANI nanosheets are attributed to the long-range ordered edge-on ?-stacking of the quinoid ring, ascribed to the ice surface-assisted vertical growth of PANI. The PANI nanosheet can be easily transferred onto various types of substrates via float-off from the ice surfaces. In addition, PANI can be patterned into any shape using predetermined masks, and this is expected to facilitate the eventual convenient and inexpensive application of conducting polymers in versatile electronic device forms.

Abstract: The present invention relates to a new method of synthesizing two-dimensional polyaniline (PANI) nanosheets using ice as a removable hard template. The method comprises polymerizing aniline on an ice surface. The synthesized PANI nanosheets show distinctly high current flows of 5.5 mA at 1 V and a high electrical conductivity of 35 S/cm, which mark a significant improvement over previous values on other PANIs reported over the past decades. These improved electrical properties of the PANI nanosheets are attributed to the long-range ordered edge-on ?-stacking of the quinoid ring, ascribed to the ice surface-assisted vertical growth of PANI. The PANI nanosheet can be easily transferred onto various types of substrates via float-off from the ice surfaces. In addition, PANI can be patterned into any shape using predetermined masks, and this is expected to facilitate the eventual convenient and inexpensive application of conducting polymers in versatile electronic device forms.

Abstract: The present invention relates to a bioelectrode including a cross-linkable organometallic polymer, and to a method for manufacturing same, and more particularly, to an electrode in which a nanostructure of the organometallic polymer is controlled to be used in bio fuel cells, biosensors, and the like. The electrode according to the present invention includes an organometal and further includes a self-assembling block copolymer and enzyme, and provides usages in bio fuel cells and biosensors.