Abstract: An embedded memory device is designed in such a manner that allows the embedded memory device to undergo the burn-in process more conveniently and efficiently without the need to use complex control timing. Moreover, the embedded memory device allows the burn-in board to be simpler than the prior art in layout structure. The embedded memory device includes the following: a memory unit having an address decoder and a sense amplifier; a control logic unit capable of generating an output of system data and an output of system address; a first counter which is driven by a system clock signal for generating an output of counter address; a second counter which is capable of generating an output of counter data; an address buffer, under control by a burn-in signal, for selecting either the system address or the counter address as memory address to the address decoder; and a data buffer, also under control by the burn-in signal, for selecting the counter data or the system data as memory data to the sense amplifier.

Abstract: A static random access memory having a structure that allow two memory cells to use a common complementary bit line. With two memory cells using a common complementary bit line, the number of necessary bit lines will be reduce by one quarter. In other words, one quarter fewer metal lines are required. This has the effect of lowering the packing density of metal lines, or increasing the product yield and the number of memory cells that can be packed within the same wafer area.

Abstract: A method of operation for shortening burn-in time. An unconnected pin in an address decoder is utilized as a dedicated burn-in pin. Through controlling the number of don't care input pins in the address decoder, the number of word line addresses for a memory that can be checked simultaneously is determined. Because the method of operation in this invention does not require changing any of the existing equipment and tooling, vast quantities of testing time and hence production cost can be saved.

Abstract: A PWL control circuit and method is provided for use on a memory device to control the high/low logic state of the wordlines connected to the memory cell array of the memory device during access operation. The memory device can be a DRAM (dynamic random-access memory) device or an SRAM (static random-access memory device). The PWL control circuit and method utilizes a feedback signal from the sense amplifier to control the high/low logic state of the wordlines of the memory device. This feature can help eliminate the problem of an early deactivation of the currently activated wordlines during access operation that would otherwise occur when using the RC delay circuit in the prior art. Therefore, even if process parameters of the memory device are changed, the reliable sensing of the data from the memory cells is not affected.