Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Abstract: A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.