Abstract: A pseudo-random switched resistor for emulating a relatively high input impedance. The switched resistor comprises a relatively low value resistor, a semiconductor switch coupled to the resistor, and a pseudo-random pulse generator coupled to the switch for controlling the on time of the switch to emulate the relatively high input impedance. The random pulse generator comprises a plurality of cascaded circuits that are coupled to a flip flop. The plurality of cascaded circuits each comprise a shift register for receiving clock signals and for generating a sequence of (2.sup.N -1) pseudo-random numbers and a terminal count pulse at the end of every sequence, an N-bit binary counter for receiving the terminal count pulse which clocks it, and an equivalence circuit for comparing the outputs of the shift register and the binary counter and for generating an output signal when there is a match.