Patents by Inventor Joydeep Mitra
Joydeep Mitra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11599699Abstract: The present disclosure relates to systems and methods for floorplanning using machine learning techniques. Embodiments may include receiving an electronic design and analyzing the electronic design using a reinforcement learning agent. Embodiments may further include recommending a first action wherein the first action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the electronic design based upon, at least in part, the first action to generate an updated electronic design. Embodiments may further include analyzing the updated electronic design using the reinforcement learning agent and recommending a second action wherein the second action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the updated electronic design based upon the second action to generate a second updated electronic design.Type: GrantFiled: February 10, 2020Date of Patent: March 7, 2023Assignee: Cadence Design Systems, Inc.Inventors: Luke Roberto, Joydeep Mitra, Taylor Elsom Hogan, Shang Li, Zachary Joseph Zumbo, John Robert Murphy
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Patent number: 10296988Abstract: An electric power system or power grid is optimized using a computer-implemented tool the represents in computer memory the optimization function and at least one constraint, which the processor operates upon using a linear programming solver algorithm. The constraints are represented in memory as data structures that include both real and reactive power terms, corresponding to at least one of a power flow model and a transmission line model. The transmission line model is represented using a piecewise linear representation. The power flow model may also include for each node in the power system a real power loss term representing transmission line loss allocated to that node.Type: GrantFiled: August 13, 2014Date of Patent: May 21, 2019Assignee: Board of Trustees of Michigan State UniversityInventor: Joydeep Mitra
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Patent number: 10097000Abstract: The analysis tool employs a computer-implemented algorithm that uses homotopy-based approaches to map the solution from the exit point to the controlling unstable equilibrium point (UEP). The computational time is reduced significantly by using an approximate exit point rather than computing an accurate exit point as it is required in finding the controlling UEPs using traditional transient stability direct methods. In addition, this method eliminates the necessity of computing the minimum gradient point (MGP) which is a key element in using Newton methods. These properties provide an advantage to homotopy-based approaches over traditional iterative methods in terms of both speed of computation and reliability of finding solutions.Type: GrantFiled: August 11, 2015Date of Patent: October 9, 2018Assignee: Board of Trustees of Michigan State UniversityInventors: Joydeep Mitra, Mohammed Ben-Idris, Niannian Cai
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Publication number: 20170220729Abstract: Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. In the coloring/grouping graph, each coloring edge connects two nodes representing layout features that must be assigned to different masks, and each grouping/coloring edge connects two nodes representing layout features that should either be grouped together for DSA (directed-self-assembly) lithography or be assigned to different masks for multiple patterning lithography. The node groups formed by nodes connected with the coloring edges are colored. Colors of the nodes in one or more of node groups connected by the grouping/coloring edges are adjusted to convert one or more of the grouping/coloring edges into the coloring edges.Type: ApplicationFiled: April 13, 2017Publication date: August 3, 2017Inventors: Fedor Pikus, Juan Andres Torres Robles, Joydeep Mitra
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Patent number: 9652581Abstract: Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. In the coloring/grouping graph, each coloring edge connects two nodes representing layout features that must be assigned to different masks, and each grouping/coloring edge connects two nodes representing layout features that should either be grouped together for DSA (directed-self-assembly) lithography or be assigned to different masks for multiple patterning lithography. The node groups formed by nodes connected with the coloring edges are colored. Colors of the nodes in one or more of node groups connected by the grouping/coloring edges are adjusted to convert one or more of the grouping/coloring edges into the coloring edges.Type: GrantFiled: June 19, 2015Date of Patent: May 16, 2017Assignee: Mentor Graphics CorporationInventors: Fedor Pikus, Juan Andres Torres Robles, Joydeep Mitra
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Publication number: 20160292345Abstract: Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. In the coloring/grouping graph, each coloring edge connects two nodes representing layout features that must be assigned to different masks, and each grouping/coloring edge connects two nodes representing layout features that should either be grouped together for DSA(directed-self-assembly) lithography or be assigned to different masks for multiple patterning lithography. The node groups formed by nodes connected with the coloring edges are colored. Colors of the nodes in one or more of node groups connected by the grouping/coloring edges are adjusted to convert one or more of the grouping/coloring edges into the coloring edges.Type: ApplicationFiled: June 19, 2015Publication date: October 6, 2016Inventors: Fedor Pikus, Juan Andres Torres Robles, Joydeep Mitra
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Patent number: 9330228Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.Type: GrantFiled: April 22, 2015Date of Patent: May 3, 2016Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, Joydeep Mitra, Yuansheng Ma, Krasnova Polina Andreevna, Yuri Granik
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Publication number: 20160041232Abstract: The analysis tool employs a computer-implemented algorithm that uses homotopy-based approaches to map the solution from the exit point to the controlling unstable equilibrium point (UEP). The computational time is reduced significantly by using an approximate exit point rather than computing an accurate exit point as it is required in finding the controlling UEPs using traditional transient stability direct methods. In addition, this method eliminates the necessity of computing the minimum gradient point (MGP) which is a key element in using Newton methods. These properties provide an advantage to homotopy-based approaches over traditional iterative methods in terms of both speed of computation and reliability of finding solutions.Type: ApplicationFiled: August 11, 2015Publication date: February 11, 2016Applicant: Board of Trustees of Michigan State UniversityInventors: Joydeep MITRA, Mohammed BEN-IDRIS, Niannian CAI
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Publication number: 20150227676Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.Type: ApplicationFiled: April 22, 2015Publication date: August 13, 2015Inventors: Juan Andres Torres Robles, Joydeep Mitra, Yuansheng Ma, Krasnova Polina Andreevna, Yuri Granik
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Publication number: 20150051744Abstract: An electric power system or power grid is optimized using a computer-implemented tool the represents in computer memory the optimization function and at least one constraint, which the processor operates upon using a linear programming solver algorithm. The constraints are represented in memory as data structures that include both real and reactive power terms, corresponding to at least one of a power flow model and a transmission line model. The transmission line model is represented using a piecewise linear representation. The power flow model may also include for each node in the power system a real power loss term representing transmission line loss allocated to that node.Type: ApplicationFiled: August 13, 2014Publication date: February 19, 2015Applicant: Board of Trustees of Michigan State UniversityInventor: Joydeep MITRA
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Patent number: 7180210Abstract: A standby generator integration system for efficiently integrating one or more standby generators into an operational power grid. The standby generator integration system includes a control center in communication with a plurality of control units. Each of the control units are in communication with a standby generator, the power grid and a contactor unit. The control unit calculates the hard minimum of the grid voltage and the generator voltage where switching is desired by summing the rectified voltages together. The control unit then initiates the closing of the contactor unit to bring the standby generator online with the power grid.Type: GrantFiled: October 10, 2003Date of Patent: February 20, 2007Inventors: Joel Jorgenson, Joydeep Mitra, Donald Stuehm, Terry Shaner
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Patent number: 6591402Abstract: Techniques for analyzing circuit designs based on assertions. An assertion is associated with a circuit structure from the circuit design. The assertion specifies a context of the circuit design in which the circuit structure is to be analyzed, an attribute associated with the circuit structure, and a constraint associated with the attribute. The present invention analyzes the circuit design based on assertions and checks to identify one or more instances of the circuit structure in the circuit design which do not satisfy the constraint specified in the assertion. An assertion may also indicate an action to be performed if the circuit structure does not satisfy the constraint specified in the assertion.Type: GrantFiled: March 17, 2000Date of Patent: July 8, 2003Assignee: Moscape, Inc.Inventors: Rajit Chandra, Joydeep Mitra, Steven B. Parks, Chandrasekhara Somanathan
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Patent number: 6449753Abstract: An automated method of analyzing crosstalk in a digital logic integrated circuit on a digital computer is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. The netlist has gate and black box invocations as well as transistor invocations. Library models are used to find driving resistances and capacitances associated with the gate and black-box invocations. For at least one potential victim wire of the plurality of wires, a subset of the wires of the chip are found to be potential aggressor wires to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire.Type: GrantFiled: March 20, 2000Date of Patent: September 10, 2002Assignee: Sun Microsystems, Inc.Inventors: Kathirgamar Aingaran, Joydeep Mitra
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Patent number: D776130Type: GrantFiled: January 15, 2015Date of Patent: January 10, 2017Assignee: ADP, LLCInventors: Vicki Contreras, Chandraprabha Rajput, Devendra Sharma, Anuradha Verma, Nagamalleswara Bodeddula, Neil DeJesus, Radhika Manthena, Nived Turai, Joydeep Mitra, Tanmay Saxena
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Patent number: D782496Type: GrantFiled: January 15, 2015Date of Patent: March 28, 2017Assignee: ADP, LLCInventors: Vicki Contreras, Chandraprabha Rajput, Devendra Sharma, Anuradha Verma, Nagamalleswara Bodeddula, Neil DeJesus, Radhika Manthena, Nived Turai, Joydeep Mitra, Tanmay Saxena