Patents by Inventor Joydeep Ray

Joydeep Ray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Engine to enable high speed context switching via on-die storage
    Patent number: 11210265
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: December 28, 2021
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
  • NON-DAIRY FOOD COMPOSITION AND PROCESS FOR PREPARATION THEREOF
    Publication number: 20210392921
    Abstract: The present invention relates to a non-dairy food composition comprising particles of an emulsion gel dispersed in a crystallized lipid; wherein the emulsion gel comprises a combination of dietary fiber; plant protein, lipid and calcium; and wherein the composition is devoid of additives. The composition of the invention is free of cholesterol, low in saturated fats and methods for making them. In a particular aspect of the present invention, the non-dairy food composition is employed as an animal fat substitute to mimic the appearance and texture of adipose tissue as well as appealing mouthfeel and texture in meat-analogues.
    Type: Application
    Filed: October 31, 2019
    Publication date: December 23, 2021
    Inventors: Isabel Fernandez Farres, Joydeep Ray, Tilman Johannes Schober
  • CONVOLUTIONAL NEURAL NETWORK OPTIMIZATION MECHANISM
    Publication number: 20210397925
    Abstract: A library of machine learning primitives is provided to optimize a machine learning model to improve the efficiency of inference operations. In one embodiment a trained convolutional neural network (CNN) model is processed into a trained CNN model via pruning, convolution window optimization, and quantization.
    Type: Application
    Filed: August 26, 2021
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Liwei Ma, Elmoustapha Ould-Ahmed-Vall, Barath Lakshmanan, Ben J. Ashbaugh, Jingyi Jin, Jeremy Bottleson, Mike B. Macpherson, Kevin Nealis, Dhawal Srivastava, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Altug Koker, Abhishek R. Appu
  • DISPLAY ENGINE SURFACE BLENDING AND ADAPTIVE TEXEL TO PIXEL RATIO SAMPLE RATE SYSTEM, APPARATUS AND METHOD
    Publication number: 20210398250
    Abstract: Systems, apparatuses and methods may provide away to blend two or more of the scene surfaces based on the focus area and an offload threshold. More particularly, systems, apparatuses and methods may provide a way to blend, by a display engine, two or more of the focus area scene surfaces and blended non-focus area scene surfaces. The systems, apparatuses and methods may include a graphics engine to render the focus area surfaces at a higher sample rate than the non-focus area scene surfaces.
    Type: Application
    Filed: April 26, 2021
    Publication date: December 23, 2021
    Inventors: Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Prasoonkumar Surti
  • NON-DAIRY CHEESE ANALOGUE AND PROCESS FOR PREPARATION THEREOF
    Publication number: 20210386086
    Abstract: The present invention relates to a non-dairy cheese analogue composition comprising dietary fiber; plant protein, lipid and calcium, wherein the composition is devoid of additives. The composition of the invention is devoid of additives comprising modified starches, hydrocolloids, emulsifiers, whitening agents, plasticizers and anti-caking agents. The invention also relates to a method preparing such compositions and uses thereof.
    Type: Application
    Filed: October 31, 2019
    Publication date: December 16, 2021
    Inventors: Joydeep Ray, Isabel Fernandez Farres
  • HARD NON-DAIRY CHEESE COMPOSITION AND PROCESS FOR PREPARATION THEREOF
    Publication number: 20210386085
    Abstract: The present invention relates to a hard non-dairy cheese composition comprising dietary fiber; flour, non-animal protein, and lipid, wherein the composition is devoid of additives, and wherein the composition has a moisture content of less than 45 wt %. The invention also relates to a method preparing such compositions and uses thereof.
    Type: Application
    Filed: October 31, 2019
    Publication date: December 16, 2021
    Inventors: Joydeep Ray, Isabel Fernandez Farres
  • AUGMENTED REALITY AND VIRTUAL REALITY FEEDBACK ENHANCEMENT SYSTEM, APPARATUS AND METHOD
    Publication number: 20210390762
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.
    Type: Application
    Filed: March 23, 2021
    Publication date: December 16, 2021
    Inventors: Chandrasekaran Sakthivel, Michael Apodaca, Kai Xiao, Altug Koker, Jeffery S. Boles, Adam T. Lake, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, James M. Holland, Prasoonkumar Surti, Jonathan Kennedy, Louis Feng, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • EFFICIENT SHARING AND COMPRESSION EXPANSION OF DATA ACROSS PROCESSING SYSTEMS
    Publication number: 20210390654
    Abstract: A mechanism is described for facilitating sharing of data and compression expansion of models at autonomous machines. A method of embodiments, as described herein, includes detecting a first processor processing information relating to a neural network at a first computing device, where the first processor comprises a first graphics processor and the first computing device comprises a first autonomous machine. The method further includes facilitating the first processor to store one or more portions of the information in a library at a database, where the one or more portions are accessible to a second processor of a computing device.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 16, 2021
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Sara S. Baghsorkhi, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Joydeep Ray
  • Separately processing regions or objects of interest from a render engine to a display engine or a display panel
    Patent number: 11200717
    Abstract: Video or graphics, received by a render engine within a graphics processing unit, may be segmented into a region of interest such as foreground and a region of less interest such as background. In other embodiments, an object of interest may be segmented from the rest of the depiction in a case of a video game or graphics processing workload. Each of the segmented portions of a frame may themselves make up a separate surface which is sent separately from the render engine to the display engine of a graphics processing unit. In one embodiment, the display engine combines the two surfaces and sends them over a display link to a display panel. The display controller in the display panel displays the combined frame. The combined frame is stored in a buffer and refreshed periodically.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventor: Joydeep Ray
  • SENSORY ENHANCED AUGEMENTED REALITY AND VIRTUAL REALITY DEVICE
    Publication number: 20210382548
    Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.
    Type: Application
    Filed: April 19, 2021
    Publication date: December 9, 2021
    Inventors: Altug Koker, Michael Apodaca, Kai Xiao, Chandrasekaran Sakthivel, Jeffery S. Boles, Adam T. Lake, James M. Holland, Pattabhiraman K, Sayan Lahiri, Radhakrishnan Venkataraman, Kamal Sinha, Ankur N. Shah, Deepak S. Vembar, Abhishek R. Appu, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall
  • Apparatus and method for improved cache utilization and efficiency on a many core processor
    Patent number: 11194722
    Abstract: Apparatus and method for improved cache utilization and efficiency on a many-core processor. An apparatus comprising: a plurality of execution units to generate cache access requests responsive to executing instructions; a pending request queue to store pending cache access requests generated by the execution units; pending queue management circuitry to compare a current cache access request with entries in the pending request queue to determine whether the current cache access request can be merged with an entry in the pending request queue and, if so, to merge the current cache access request with the entry.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: Bharath Narasimha Swamy, Joydeep Ray, Rama Kishan Malladi, James Valerio, Abhishek Appu
  • SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THREAD GROUPS
    Publication number: 20210373899
    Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
    Type: Application
    Filed: February 11, 2021
    Publication date: December 2, 2021
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • MATRIX OPERATION OPTIMIZATION MECHANISM
    Publication number: 20210374209
    Abstract: An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 2, 2021
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Fangwen Fu, Dhiraj D. Kalamkar, Sasikanth Avancha
  • SECTOR CACHE FOR COMPRESSION
    Publication number: 20210374062
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, David Puffer, Prasoonkumar Surti, Lakshminarayanan Striramassarma, Vasanth Ranganathan, Kiran C. Veernapu, Balaji Vembu, Pattabhiraman K
  • SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
    Publication number: 20210374897
    Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 2, 2021
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Scott Janus, Varghese George, Subramaniam Maiyuran, Altug Koker, Abhishek Appu, Prasoonkumar Surti, Vasanth Ranganathan, Andrei Valentin, Ashutosh Garg, Yoav Harel, Arthur Hunter, JR., SungYe Kim, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, William Sadler, Lakshminarayanan Striramassarma, Vikranth Vemulapalli
  • Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading
    Patent number: 11182296
    Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Andrew T. Lauritzen, Gabor Liktor, Tomer Bar-On, Hugues Labbe, John G. Gierach, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Altug Koker
  • Microcontroller-based flexible thread scheduling launching in computing environments
    Patent number: 11175949
    Abstract: A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: November 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Kiran C. Veernapu, Kamlesh Pillai, James Valerio, Joydeep Ray, Abhishek Appu
  • Switching crossbar for graphics pipeline
    Patent number: 11176083
    Abstract: A shared local memory data crossbar may be implemented in multiple stages. With this approach, the number of multiplexer cells can be reduced by fifty percent (50%) or more in some embodiments.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, James A. Valerio, Altug Koker, Abhishek R. Appu, Vasanth Ranganathan
  • System, apparatus and method for increasing performance in a processor during a voltage ramp
    Patent number: 11175719
    Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Altug Koker, Abhishek R. Appu, Bhushan M. Borole, Wenyin Fu, Kamal Sinha, Joydeep Ray
  • HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK
    Publication number: 20210349715
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu, Subramaniam Maiyuran, Prasoonkumar Surti, Guei-Yuan Lueh, David Puffer, Supratim Pal, Eric J. Hoekstra, Travis T. Schluessler, Linda L. Hurd