Patents by Inventor Joydeep Ray

Joydeep Ray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Neural network optimization mechanism
    Patent number: 10929749
    Abstract: An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: February 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Narayan Srinivasa, Joydeep Ray, Nicolas C. Galoppo Von Borries, Ben Ashbaugh, Prasoonkumar Surti, Feng Chen, Barath Lakshmanan, Elmoustapha Ould-Ahmed-Vall, Liwei Ma, Linda L. Hurd, Abhishek R. Appu, John C. Weast, Sara S. Baghsorkhi, Justin E. Gottschlich, Chandrasekaran Sakthivel, Farshad Akhbari, Dukhwan Kim, Altug Koker, Nadathur Rajagopalan Satish
  • Multi-sample stereo renderer
    Patent number: 10930046
    Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws
  • CONTROL SURFACE ACCESS USING FLAT MEMORY MAPPING
    Publication number: 20210049098
    Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.
    Type: Application
    Filed: October 12, 2020
    Publication date: February 18, 2021
    Applicant: Intel Corporation
    Inventors: NIRANJAN L. COORAY, Altug Koker, Vidhya Krishnan, Ronald W. Silvas, John H. Feit, Prasoonkumar Surti, Joydeep Ray, Abhishek R. Appu
  • APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE
    Publication number: 20210049728
    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.
    Type: Application
    Filed: May 5, 2020
    Publication date: February 18, 2021
    Inventors: Joydeep Ray, Abhishek R. Appu, Altug Koker, Balaji Vembu
  • FIELD RECOVERY OF GRAPHICS ON-DIE MEMORY
    Publication number: 20210050070
    Abstract: Systems, apparatuses and methods may provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion may be substituted for the one or more failed memory cells.
    Type: Application
    Filed: August 28, 2020
    Publication date: February 18, 2021
    Inventors: Altug Koker, Travis T. Schluessler, Ankur N. Shah, Abhishek R. Appu, Joydeep Ray, Jonathan Kennedy
  • Person tracking and privacy and acceleration of data using autonomous machines
    Patent number: 10922553
    Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: February 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Mayuresh M. Varerkar, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Sherine Abdelhak, Sachin Godse, Farshad Akhbari, Narayan Srinivasa, Altug Koker, Nadathur Rajagopalan Satish, Dukhwan Kim, Feng Chen, Abhishek R. Appu, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Scatter gather engine
    Patent number: 10922869
    Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: February 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Murali Ramadoss, David I. Standring, Shruti A. Sethi, Jeffrey S. Frizzell, Alan M. Curtis, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • Scheduling of threads for execution utilizing load balancing of thread groups
    Patent number: 10922085
    Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: February 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • POWER SAVINGS FOR NEURAL NETWORK ARCHITECTURE WITH ZERO ACTIVATIONS DURING INFERENCE
    Publication number: 20210041934
    Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Applicant: Intel Corporation
    Inventors: KINCHIT DESAI, SANJEEV JAHAGIRDAR, PRASOONKUMAR SURTI, JOYDEEP RAY
  • PROGRESSIVE MULTISAMPLE ANTI-ALIASING
    Publication number: 20210042983
    Abstract: One embodiment provides for a data processing system comprising a memory module to store a multisample render target, the multisample render target to store multiple sample locations for each pixel in a set of pixels and a general-purpose graphics processor including a hardware graphics rendering pipeline to generate pixel color data to be output to the multisample render target, a multisample antialiasing compressor to request allocation of one or more planes to store color data for a set of sample locations of a pixel in the set of pixels, and a memory allocator to allocate memory to store color data associated with the multisample render target. The memory allocator can merge a memory allocation for multiple pixels having a sample associated with a same color value.
    Type: Application
    Filed: October 13, 2020
    Publication date: February 11, 2021
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Prasoonkumar Surti, Joydeep Ray, Michael J. Norris
  • AVOID CACHE LOOKUP FOR COLD CACHE
    Publication number: 20210034540
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 4, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Prasoonkumar Surti, Kamal Sinha, Kiran C. Veernapu, Balaji Vembu
  • INTERCONNECT FABRIC LINK WIDTH REDUCTION TO REDUCE INSTANTANEOUS POWER CONSUMPTION
    Publication number: 20210034135
    Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.
    Type: Application
    Filed: August 13, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Mohammed Tameem, Altug Koker, Kiran C. Veernapu, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Travis T. Schluessler, Jonathan Kennedy
  • ON DEMAND MSAA RESOLVE DURING LENS CORRECTION AND/OR OTHER POST-PROCESSING PHASES
    Publication number: 20210035270
    Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.
    Type: Application
    Filed: July 15, 2020
    Publication date: February 4, 2021
    Inventors: Tomer Bar-On, Hugues Labbe, Adam T. Lake, Kai Xiao, Ankur N. Shah, Johannes Guenther, Abhishek R. Appu, Joydeep Ray, Deepak S. Vembar, ElMoustapha Ould-Ahmed-Vall
  • SPARSE OPTIMIZATOINS FOR A MATRIX ACCELERATOR ARCHITECTURE
    Publication number: 20210035258
    Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.
    Type: Application
    Filed: October 6, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Scott Janus, Varghese George, Subramaniam Maiyuran, Altug Koker, Abhishek Appu, Prasoonkumar Surti, Vasanth Ranganathan, Andrei Valentin, Ashutosh Garg, Yoav Harel, Arthur Hunter, JR., SungYe Kim, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, William Sadler, Lakshminarayanan Striramassarma, Vikranth Vemulapalli
  • LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT
    Publication number: 20210035259
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
    Type: Application
    Filed: July 16, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Vasanth Ranganathan, Saikat Mandal, Karol A. Szerszen, Saurabh Sharma, Vamsee Vardhan Chivukula, Abhishek R. Appu, Joydeep Ray, Prasoonkumar Surti, Altug Koker
  • PAGE FAULTING AND SELECTIVE PREEMPTION
    Publication number: 20210035254
    Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
    Type: Application
    Filed: July 9, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Altug Koker, Ingo Wald, David Puffer, Subramaniam M. Maiyuran, Prasoonkumar Surti, Balaji Vembu, Guei-Yuan Lueh, Murali Ramadoss, Abhishek R. Appu, Joydeep Ray
  • Frequent Data Value Compression for Graphics Processing Units
    Publication number: 20210035257
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Application
    Filed: August 5, 2020
    Publication date: February 4, 2021
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Efficient multi-context thread distribution
    Patent number: 10908905
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Balaji Vembu, Abhishek R. Appu, Kamal Sinha, Prasoonkumar Surti, Kiran C. Veernapu
  • Collaborative multi-user virtual reality
    Patent number: 10908865
    Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Deepak S. Vembar, Atsuo Kuwahara, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hughes Labbe, Altug Koker, Michael Apodaca, Kai Xiao, Jeffery S. Boles, Adam T. Lake, David M. Cimini, Balaji Vembu, Elmoustapha Ould-Ahmed-Vall, Jacek Kwiatkowski, Philip R. Laws, Ankur N. Shah, Abhishek R. Appu, Joydeep Ray, Wenyin Fu, Nikos Kaburlasos, Prasoonkumar Surti, Bhushan M. Borole
  • Optimizing memory address compression
    Patent number: 10909037
    Abstract: A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cacheline addresses such that each of a set of slot addresses in a group have a memory cacheline address in common between them. The method may further include outputting the memory cacheline addresses.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: February 2, 2021
    Assignee: INTEL CORPOR ATION
    Inventors: Joydeep Ray, Abhishek R. Appu, Altug Koker, James A. Valerio, Prasoonkumar Surti