Patents by Inventor Jozef C. Mitros
Jozef C. Mitros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8946805Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.Type: GrantFiled: August 6, 2009Date of Patent: February 3, 2015Assignee: Texas Instruments IncorporatedInventors: Jozef C. Mitros, Keith Jarreau, Pinghai Hao
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Patent number: 7919368Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.Type: GrantFiled: May 29, 2009Date of Patent: April 5, 2011Assignee: Texas Instruments IncorporatedInventors: Xiaoju Wu, Jozef C. Mitros
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Publication number: 20100032744Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.Type: ApplicationFiled: August 6, 2009Publication date: February 11, 2010Applicant: Texas Instruments IncorporatedInventors: Jozef C. Mitros, Keith Jarreau, Pinghai Hao
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Patent number: 7279738Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.Type: GrantFiled: June 2, 2005Date of Patent: October 9, 2007Assignee: Texas Instruments IncorporatedInventors: Imran M. Khan, Louis N. Hutter, James (Bob) Todd, Jozef C. Mitros, William E. Nehrer
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Patent number: 6979615Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.Type: GrantFiled: September 12, 2002Date of Patent: December 27, 2005Assignee: Texas Instruments IncorporatedInventors: Imran M. Khan, Louis N. Hutter, James Todd, Jozef C. Mitros, William E. Nehrer
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Patent number: 6930005Abstract: A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination.Type: GrantFiled: December 2, 2003Date of Patent: August 16, 2005Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Jozef C. Mitros, Imran Khan
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Patent number: 6897113Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).Type: GrantFiled: June 8, 2004Date of Patent: May 24, 2005Assignee: Texas Instruments IncorporatedInventor: Jozef C. Mitros
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Patent number: 6873021Abstract: A drain-extended MOS transistor in a semiconductor wafer (300) of a first conductivity type comprises a first well (315) of the first conductivity type, operable as the extension of the transistor drain (305) of the first conductivity type, and covered by a first insulator (312) having a first thickness, and further a second well (302) of the opposite conductivity type, intended to contain the transistor source (304) of the first conductivity type, and covered by a second insulator (311) thinner than said first insulator (312). First and second wells form a junction (330) that terminates (320, 321) at the second insulator. The first well has a region (360) in the proximity of the junction termination, which has a higher doping concentration than the remainder of the first well and extends not deeper than the first insulator thickness.Type: GrantFiled: December 2, 2003Date of Patent: March 29, 2005Assignee: Texas Instruments IncorporatedInventors: Jozef C. Mitros, Imran Khan, Taylor R. Efland
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Publication number: 20040217415Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).Type: ApplicationFiled: June 8, 2004Publication date: November 4, 2004Inventor: Jozef C. Mitros
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Patent number: 6806541Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.Type: GrantFiled: March 1, 2004Date of Patent: October 19, 2004Assignee: Texas Instruments IncorporatedInventors: Lily X. Springer, Binghua Hu, Chin-Yu Tsai, Jozef C. Mitros
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Publication number: 20040175891Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).Type: ApplicationFiled: March 15, 2004Publication date: September 9, 2004Applicant: Texas Instruments Deutschland GmbHInventors: Jozef C. Mitros, Imran Khan, William Nehrer, Lou Hutter, Dirk Preikszat
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Publication number: 20040169253Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.Type: ApplicationFiled: March 1, 2004Publication date: September 2, 2004Inventors: Lily X. Springer, Binghua Hu, Chin-Yu Tsai, Jozef C. Mitros
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Patent number: 6770933Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).Type: GrantFiled: December 11, 2002Date of Patent: August 3, 2004Assignee: Texas Instruments IncorporatedInventor: Jozef C. Mitros
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Publication number: 20040113198Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Applicant: Texas Instruments IncorporatedInventor: Jozef C. Mitros
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Patent number: 6747308Abstract: An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.Type: GrantFiled: December 30, 2002Date of Patent: June 8, 2004Assignee: Texas Instruments IncorporatedInventors: Jozef C. Mitros, Lily Springer, Roland Bucksch
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Patent number: 6734491Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).Type: GrantFiled: December 30, 2002Date of Patent: May 11, 2004Assignee: Texas Instruments Deutschland GmbHInventors: Jozef C. Mitros, Imran Khan, William Nehrer, Lou Hutter, Dirk Preikszat
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Patent number: 6730569Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.Type: GrantFiled: October 25, 2001Date of Patent: May 4, 2004Assignee: Texas Instruments IncorporatedInventors: Lily X. Springer, Binghua Hu, Chin-Yu Tsai, Jozef C. Mitros
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Publication number: 20040053455Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.Type: ApplicationFiled: September 12, 2002Publication date: March 18, 2004Applicant: Texas Instruments IncorporatedInventors: Imran M. Khan, Louis N. Hutter, James (Bob) Todd, Jozef C. Mitros, William E. Nehrer
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Publication number: 20030137005Abstract: An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.Type: ApplicationFiled: December 30, 2002Publication date: July 24, 2003Inventors: Jozef C. Mitros, Lily Springer, Roland Bucksch
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Publication number: 20030127694Abstract: An integrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50),(140) and drain regions (55),(145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70),(80) serve as the drain extension regions of the transistors.Type: ApplicationFiled: December 13, 2002Publication date: July 10, 2003Inventors: Alec Morton, Taylor Efland, Chin-Yu Tsai, Jozef C. Mitros, Dan M. Mosher, Sam Shichijo, Keith Kunz