Abstract: A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made.

Abstract: Disclosed is a mobile data carrier comprising a data-processing circuit; and a supply unit (1) to apply electric energy to power supply terminals for operating the data-processing circuit from an external energy source and (2) controlling voltage and current at external access points of the data carrier, wherein the supply unit including a voltage-limiting control circuit arranged in parallel to the power supply terminals of the data-processing circuit, and a current control device which, with respect to the supply of energy to the data-processing circuit, is arranged in series with the parallel arrangement of the voltage-limiting control circuit and the data-processing circuit.

Abstract: Arithmetic unit for multiplying long integers modulo M and R.S.A. converter provided with such multiplication device.A systolized and modular arithmetic device has a control module, followed by a series arrangement of processing module, followed by a tail module. For multiplying an integer P and an integer Q modulo a third integer M, a provisional product is incremented each time with Q for a -1- bit in P, preceding by a doubling of the product. For a -0- bit only the doubling ensues. Normalizing mod M is effected by adding the complement of M, W, under control of propagated carry values. A similar procedure is proposed for exponentiation of Q. F.

Abstract: A multiple redundant clock system comprises at least n=4 clocks and is self-synchronizing and fault tolerant against the failure of at the most 1/2(n-1) clocks. Each clock comprises an oscillator circuit which activates a dividing circuit at the end of each period in order to form its own clock signal on the output of the dividing circuit. Each clock furthermore comprises a deviation-determining device which compares the own clock signal with the clock signals originating from the other clocks in the system. When an excessively large number of the other clock signals deviate during the first half of the (own) period, the own oscillator circuit is decelerated. When an excessively large number of the other clock signals deviate during the second half of the own period, the own oscillator circuit is accelerated.

Abstract: A processor system having one or more stations (22, 24, 26) which are interconnected by a general communication network (20). Each station has one or more processors (34, 36). Superprocesses (74, 76, 78) which have one or more processes (80-90) can be executed in the stations. Each superprocess is provided with mail-box space (50, 52, 54) for communication with the environment, in which mail-box space the relevant superprocess and other superprocesses can write but in which only the relevant superprocess itself can read. Processes within the same superprocess have variable data in common, but their register stacks are private. Each mail-box is provided with a filling indicator. In the case of a read operation in an empty mail-box space, a wait signal is issued for the initiating process; write operations in a full mail-box space produce an error signal. There is also provided a job control system for allocating jobs among the stations by way of an application load file.

Abstract: A time switching method and apparatus for exchanging data words from a sequence of time slots in an incoming time-division multiplex frame to any other sequence of time slots an outgoing time-division multiplex frame. A data word in a given time slot s in an incoming frame is stored in a memory at an address A(s) which is equal to the number of time slots D.sub.j in an outgoing frame for which j is less than s and for which D.sub.j exceeds D(s). The data word already in the memory location address A(s) and the data words in addresses higher than that address are each shifted to the next higher address. Data words at memory addresses lower than A(s) are maintained at such addresses.

Abstract: A device for the processing of a data base consisting of a sequence of data records, having a reference memory (140) for a reference data record and a mask memory (142) for a mask data record. In reaction to the successively received data of a data record, these memories can be read in order to activate a comparison. There is provided an indicator element (160) which has a state "provisionally correct" and which is activated by a starting signal produced by the reception of a data record. If the comparison indicates that an impermissible relationship exists between the content of an element of the data record received and the corresponding element of the reference data record, the indicator element is set to the state "incorrect". The data record received is meanwhile stored in a data buffer (100,102). At the end of the reception, the state of the indicator element indicates whether or not the data record may be applied to a user.

Abstract: The invention relates to a broad-band, time-division multiplex, token-passing, ring local area network, with which both circuit-switched and packet-switched traffic, namely data, text, picture and speech traffic can be supported. The invention has for its object to provide a method of transmitting digital information in a ring having a comparatively high transmission capacity with which rapid access to the common ring transmission means can be obtained, without however high requirements being imposed on the processing speed of the stations. According to the invention this is in principle achieved by means of a method which guarantees that per time-division multiplex frame only one time slot, which is known to the station, needs to be accessed.

Abstract: A data buffer memory of the "first-in, first-out" type, having a fixed input by which data are applied to the buffer, and an output bus by which data are extracted from the buffer. The buffer includes logic means whereby a variable output location can be selected. The logic means determines by means of status signals in cooperation with signals applied from outside the buffer, where data are read from the buffer and, if necessary, when data in the buffer are to be shifted further from the input location.

Abstract: A commutation device for the selective control of data transport. At least two data inputs and data outputs, each of the latter having a buffer for storing a data word. A number of possibilities of data transport can be selectively controlled, four for a single connection and two different ones for pair-wise connection. Seven input control lines are provided, two lines for receiving a signal which indicates whether information is present on the associated input line, two lines for indicating the selected output buffer, two erase lines for making a data buffer freely accessible after output of data from the data buffer, and one priority line for granting priority to one of the two input lines if both lines select the same data buffer. There are four output control lines, two lines which indicate that the data present on the input lines have been taken up in the selected output buffer, and two lines which indicate whether an output buffer contains data.

Abstract: A data buffer memory for the first-in, first-out type, having an input bus by which data are supplied to the buffer, and a fixed output from which data are transferred from the buffer. Each section of the buffer includes logic whereby a variable input location can be selected. Status signals are used to determine, in cooperation with signals supplied from outside the buffer, the location where data are to be written in the buffer and when these data in the buffer must be shifted to the output.

Abstract: A data buffer memory of the "first-in, first-out" type, having an input bus by which data are applied to the buffer and an output bus by which data are taken up from the buffer. The buffer includes logic means whereby a variable input location and a variable output location can be selected. The logic means are provided for each section of the buffer and use status signals in co-operation with signals applied from outside the buffer, to determine where data are to be written in the buffer and where data are to be read from the buffer.