Patents by Inventor Jozefus Godefridus Gerardus Van Gisbergen

Jozefus Godefridus Gerardus Van Gisbergen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor layout modification method based on design rule and user constraints
    Patent number: 8266567
    Abstract: A method of modification of a semiconductor layout is provided. The layout comprises objects of semiconductor material with corners and edges. The method comprises a step of receiving (61) a set of proximities, triggers and design rules, the proximities indicating relations between neighboring edges and/or corners, the triggers defining boundaries for the modification within which boundaries the proximities are valid, the design rules describing physical requirements for the semiconductor layout. The method further comprises a step of generating (62) a set of constraints, based on the received proximities, triggers and design rules, each constraint in the set of constraints defining a limit within which the semiconductor layout may be modified without changing the proximities. Then the set of constraints to obtain a modified semiconductor layout is solved (63).
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: September 11, 2012
    Assignee: Sagantec Israel Ltd.
    Inventors: Farid El Yahyaoui, Jozefus Godefridus Gerardus Van Gisbergen
  • SEMICONDUCTOR LAYOUT MODIFICATION METHOD BASED ON DESIGN RULE AND USER CONSTRAINTS
    Publication number: 20100199235
    Abstract: A method of modification of a semiconductor layout is provided. The layout comprises objects of semiconductor material with corners and edges. The method comprises a step of receiving (61) a set of proximities, triggers and design rules, the proximities indicating relations between neighboring edges and/or corners, the triggers defining boundaries for the modification within which boundaries the proximities are valid, the design rules describing physical requirements for the semiconductor layout. The method further comprises a step of generating (62) a set of constraints, based on the received proximities, triggers and design rules, each constraint in the set of constraints defining a limit within which the semiconductor layout may be modified without changing the proximities. Then the set of constraints to obtain a modified semiconductor layout is solved (63).
    Type: Application
    Filed: June 30, 2008
    Publication date: August 5, 2010
    Applicant: SAGANTEC ISRAEL LTD
    Inventors: Farid El Yahyaoui, Jozefus Godefridus Gerardus Van Gisbergen