Abstract: A method for manufacturing a semiconductor structure including the following steps is provided. First, a first insulating layer with a conductive contact is formed over a substrate, and a second insulating layer having an opening is formed on the first insulating layer, wherein the opening corresponds to and exposes a top surface of the conductive contact. A conductive line structure is formed in the opening, wherein a contact void is formed between the second insulating layer and the conductive line structure, and then a plasma oxide layer is conformally deposited over the substrate. Then, a wet cleaning process is performed by using an aqueous solution containing negatively charged ions. A capping layer is formed on the plasma oxide layer, the capping layer filling the contact void, and an etching back process to remove the capping layer above the contact void.

Abstract: A method for manufacturing a semiconductor structure is provided. First, a first insulating layer is formed over a substrate, and a second insulating layer having an opening is formed over the first insulating layer. A conductive line structure is formed in the opening of the second insulating layer, thereby forming a contact void between the second insulating layer and the conductive line structure. A plasma oxide layer is conformally formed over the conductive line structure, the first insulating layer, and the contact void. A nitride capping layer is formed over the plasma oxide layer to fill the contact void. Then, nitrogen ions are introduced into a surface of the nitride capping layer surrounding the conductive line structure. An etching back process is performed to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the first insulating layer and the conductive line structure.

Abstract: A method for manufacturing a semiconductor device includes: forming an isolation member defining an active region in a substrate; forming a first insulating layer having a bit line contact over the substrate; forming a second insulating layer having a bit line opening on the first insulating layer; forming a bit line structure in the bit line opening, the bit line structure being electrically connecting to the bit line contact, and a contact void being formed surrounding the bit line structure and exposing a portion of the bit line contact; conformally forming a nitride spacer layer over the bit line structure, the second insulating layer, and the conductive contact; conformally forming a plasma oxide layer over the nitride spacer layer; and performing a wet cleaning process by using an aqueous solution containing negatively charged ions.

Abstract: The present disclosure provides a semiconductor memory device. The semiconductor memory device comprises a substrate, which includes a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer, wherein the substrate includes a trench between the storage area and the peripheral area, the trench is filled with a nitride material, and the substrate further comprises a first oxide layer above the nitride material in the trench and on the landing pad, a nitride layer above the first oxide layer, and a second layer above the nitride layer.

Abstract: A method for manufacturing a semiconductor structure is provided. First, a first insulating layer is formed over a substrate, and a second insulating layer having an opening is formed over the first insulating layer. A conductive line structure is formed in the opening of the second insulating layer, thereby forming a contact void between the second insulating layer and the conductive line structure. A plasma oxide layer is conformally formed over the conductive line structure, the first insulating layer, and the contact void. A nitride capping layer is formed over the plasma oxide layer to fill the contact void. Then, nitrogen ions are introduced into a surface of the nitride capping layer surrounding the conductive line structure. An etching back process is performed to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the first insulating layer and the conductive line structure.

Abstract: A method for manufacturing a semiconductor structure is provided. First, a first insulating layer is formed over a substrate, and a second insulating layer having an opening is formed over the first insulating layer. A conductive line structure is formed in the opening of the second insulating layer, thereby forming a contact void between the second insulating layer and the conductive line structure. A plasma oxide layer is conformally formed over the conductive line structure, the first insulating layer, and the contact void. A nitride capping layer is formed over the plasma oxide layer to fill the contact void. Then, nitrogen ions are introduced into a surface of the nitride capping layer surrounding the conductive line structure. An etching back process is performed to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the first insulating layer and the conductive line structure.

Abstract: The present disclosure provides to a semiconductor memory device. The semiconductor memory device includes a substrate having a cell area and a peripheral area; and a first bit line structure disposed on and protruding from a surface of the cell area. The first bit line structure is sandwiched by a pair of air gaps and a barrier layer is conformally overlaying the air gaps adjacent to the sidewalls of the first bit line structure and the cell area. The first bit line structure has a sidewall and an ascending top portion, and a landing pad is disposed over the ascending top portion and the sidewalls of the first bit line structure. The landing pad has an inclined surface corresponding to the ascending top portion of the first bit line structure.

Abstract: A method for manufacturing a semiconductor structure including the following steps is provided. First, a first insulating layer with a conductive contact is formed over a substrate, and a second insulating layer having an opening is formed on the first insulating layer, wherein the opening corresponds to and exposes a top surface of the conductive contact. A conductive line structure is formed in the opening, wherein a contact void is formed between the second insulating layer and the conductive line structure, and then a plasma oxide layer is conformally deposited over the substrate. Then, a wet cleaning process is performed by using an aqueous solution containing negatively charged ions. A capping layer is formed on the plasma oxide layer, the capping layer filling the contact void, and an etching back process to remove the capping layer above the contact void.

Abstract: A method for manufacturing a semiconductor device includes: forming an isolation member defining an active region in a substrate; forming a first insulating layer having a bit line contact over the substrate; forming a second insulating layer having a bit line opening on the first insulating layer; forming a bit line structure in the bit line opening, the bit line structure being electrically connecting to the bit line contact, and a contact void being formed surrounding the bit line structure and exposing a portion of the bit line contact; conformally forming a nitride spacer layer over the bit line structure, the second insulating layer, and the conductive contact; conformally forming a plasma oxide layer over the nitride spacer layer; and performing a wet cleaning process by using an aqueous solution containing negatively charged ions.

Abstract: The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C2F6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

Abstract: The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity; etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.

Abstract: The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity; etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.

Abstract: The present disclosure provides to a semiconductor memory device. The semiconductor memory device includes a substrate having a cell area and a peripheral area; and a first bit line structure disposed on and protruding from a surface of the cell area. The first bit line structure is sandwiched by a pair of air gaps and a barrier layer is conformally overlaying the air gaps adjacent to the sidewalls of the first bit line structure and the cell area. The first bit line structure has a sidewall and an ascending top portion, and a landing pad is disposed over the ascending top portion and the sidewalls of the first bit line structure. The landing pad has an inclined surface corresponding to the ascending top portion of the first bit line structure.

Abstract: The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C2F6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

Abstract: The present disclosure provides a semiconductor memory device. The semiconductor memory device comprises a substrate, which includes a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer, wherein the substrate includes a trench between the storage area and the peripheral area, the trench is filled with a nitride material, and the substrate further comprises a first oxide layer above the nitride material in the trench and on the landing pad, a nitride layer above the first oxide layer, and a second layer above the nitride layer.

Abstract: The present disclosure provides a semiconductor memory device and a method for manufacturing the semiconductor memory device. The method includes steps of: providing a substrate including a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer; forming a trench between the storage area and the peripheral area; filling the trench with a nitride material; forming a first oxide layer above the nitride material in the trench and on the landing pad; forming a nitride layer above the first oxide layer; and forming a second oxide layer above the nitride layer.