Abstract: A frequency synthesizing device includes a voltage-controlled oscillator receiving an adjusting signal and generating an output signal according to the adjusting signal. A feedback frequency divider having a plurality of divisor values receives the output signal and generates a feedback signal after performing frequency dividing. An automatic frequency calibration circuit of the frequency synthesizing device includes a first frequency divider receiving a reference frequency, and a second frequency divider receiving the feedback signal. A comparator of the automatic frequency calibration circuit receives and compares outputs from the first frequency divider and the second frequency divider in a predetermined period to generate a comparing result. A state machine outputs the adjusting signal according to the comparing result in a calibration mode.

Abstract: A frequency synthesizing device includes a voltage-controlled oscillator receiving an adjusting signal and generating an output signal according to the adjusting signal. A feedback frequency divider having a plurality of divisor values receives the output signal and generates a feedback signal after performing frequency dividing. An automatic frequency calibration circuit of the frequency synthesizing device includes a first frequency divider receiving a reference frequency, and a second frequency divider receiving the feedback signal. A comparator of the automatic frequency calibration circuit receives and compares outputs from the first frequency divider and the second frequency divider in a predetermined period to generate a comparing result. A state machine outputs the adjusting signal according to the comparing result in a calibration mode.

Abstract: The present invention relates to a duobinary transceiver. Specifically, the duobinary transceiver circuit proposed by the invention provides a new circuit configure of a precoder in a typical transceiver and a decoder in a typical receiver, based on a conventional transceiver including a transmitter, a transmission medium, and a receiver.

Abstract: The phase-frequency detector (PFD) includes a frequency detector (FD) arranged to receive orthogonal signal pairs of a reference signal and a feedback signal and estimate a frequency error between a reference signal and a feedback signal; a FD voltage-to-current converter arranged to convert the frequency error into a first current; a phase detector (PD) arranged to receive the orthogonal signal pairs and estimate a phase error between the reference signal and the feedback signal, and a PD voltage-to-current converter arranged to convert the phase error into a second current.

Abstract: The phase locked loop has a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal. The 3-stage frequency divider comprises three cascaded frequency dividers with different rangers of operating frequencies.

Abstract: The phase-frequency detector (PFD) includes a frequency detector (FD) arranged to receive orthogonal signal pairs of a reference signal and a feedback signal and estimate a frequency error between a reference signal and a feedback signal; a FD voltage-to-current converter arranged to convert the frequency error into a first current; a phase detector (PD) arranged to receive the orthogonal signal pairs and estimate a phase error between the reference signal and the feedback signal, and a PD voltage-to-current converter arranged to convert the phase error into a second current.

Abstract: The phase locked loop has a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal. The 3-stage frequency divider comprises three cascaded frequency dividers with different rangers of operating frequencies.

Abstract: A phase locked loop, voltage controlled oscillator, and phase-frequency detector are provided. The phase locked loop comprises a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal.

Abstract: A signal generating circuit for generating an output signal is provided. A phase detection circuit is arranged to detect a phase difference between an input reference signal and a feedback signal, and generate a control signal according to the phase difference. An injected controlled oscillator is arranged to receive the control signal and an injection signal and generate the output signal according to the control signal and the injection signal. A frequency of the output signal is proportional to a frequency of the input reference signal, and a frequency of the injection signal does not equal to the frequency of the output signal.

Abstract: The present invention relates to a duobinary transceiver. Specifically, the duobinary transceiver circuit proposed by the invention provides a new circuit configure of a precoder in a typical transceiver and a decoder in a typical receiver, based on a conventional transceiver including a transmitter, a transmission medium, and a receiver.

Abstract: A phase locked loop, voltage controlled oscillator, and phase-frequency detector are provided. The phase locked loop comprises a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal.

Abstract: A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 ?m CMOS technology.

Abstract: A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 &mgr;m CMOS technology.