Patents by Inventor JR-Wei LIN

JR-Wei LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11474301
    Abstract: A device is provided. The device may be an optical device, a light coupling device, or a tunable light coupling device. The device includes a first portion, a lens, a light emitting element, and a waveguide. The first portion is disposed adjacent to a surface of a substrate and has a first side and a second side opposite to the first side. The light emitting element is disposed adjacent to the second side of the first portion. The lens is disposed adjacent to the first side of the first portion and between the light emitting element and the waveguide.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: October 18, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Feng You, Jr-Wei Lin, Chieh-Chen Fu, Kao-Ming Su, Chen Yuan Weng
  • Publication number: 20220214488
    Abstract: A device is provided. The device may be an optical device, a light coupling device, or a tunable light coupling device. The device includes a first portion, a lens, a light emitting element, and a waveguide. The first portion is disposed adjacent to a surface of a substrate and has a first side and a second side opposite to the first side. The light emitting element is disposed adjacent to the second side of the first portion. The lens is disposed adjacent to the first side of the first portion and between the light emitting element and the waveguide.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 7, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Feng YOU, Jr-Wei LIN, Chieh-Chen FU, Kao-Ming SU, Chen Yuan Weng
  • Publication number: 20220196918
    Abstract: An optoelectronic structure includes a substrate, an electronic die and a photonic die. The electronic die is disposed on the substrate and includes a first surface, wherein the first surface is configured to support an optical component. The photonic die is disposed on the first surface of the electronic die and has an active surface toward the first surface of the electronic die and a side surface facing the optical component.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Mei-Ju LU
  • Publication number: 20220196934
    Abstract: A device is provided. The device may be an optical device, a light coupling device, or a device containing an optical structure. The device includes a waveguide, a cladding, and a light coupling material. The light coupling material is disposed adjacent to the waveguide and has a first surface and a second surface, where the second surface is disposed further away from the waveguide than the first surface and a thickness of the second surface is greater than that of the first surface.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Sin-Yuan MU, Mei-Ju LU
  • Publication number: 20220181264
    Abstract: An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Jr-Wei LIN
  • Publication number: 20220084972
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
  • Patent number: 11257763
    Abstract: An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: February 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Ju Lu, Jr-Wei Lin
  • Patent number: 11183474
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Ju Lu, Chi-Han Chen, Chang-Yu Lin, Jr-Wei Lin, Chih-Pin Hung
  • Patent number: 11152529
    Abstract: A semiconductor package structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a substrate and a circuit. The substrate has a first portion and a second portion. A first thickness of the first portion is greater than a second thickness of the second portion. The circuit is disposed on the second portion of the substrate. The second semiconductor device is disposed on the circuit of the first semiconductor device.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 19, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jr-Wei Lin
  • Patent number: 11145621
    Abstract: A semiconductor package device comprises a substrate, a first electronic component, a first encapsulant, a second electronic component, and a first conductive trace. The substrate has a first surface. The first electronic component is on the first surface of the substrate. The first encapsulant is on the first surface of the substrate and covers the first electronic component. The second electronic component is on the first encapsulant. The first conductive trace is within the first encapsulant. The first conductive trace is electrically connected to the second electronic component.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jr-Wei Lin, Chia-Cheng Liu, Chien-Feng Chan
  • Publication number: 20210175385
    Abstract: A semiconductor package structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a substrate and a circuit. The substrate has a first portion and a second portion. A first thickness of the first portion is greater than a second thickness of the second portion. The circuit is disposed on the second portion of the substrate. The second semiconductor device is disposed on the circuit of the first semiconductor device.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Jr-Wei LIN
  • Publication number: 20210167016
    Abstract: An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 3, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Jr-Wei LIN
  • Publication number: 20210134751
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
  • Publication number: 20200098700
    Abstract: A semiconductor package device includes a substrate, a sealant, a trench, a spacer and a conductive material. The substrate includes a first surface, a second surface opposite the first surface, and a lateral surface extending from the first surface to the second surface. The sealant is disposed on the first surface of the substrate and includes a first surface and a second surface opposite the first surface. The trench passes through the sealant and includes a first portion adjacent to the first surface of the sealant and a second portion between the first portion and the substrate. A width of the first portion is greater than a width of the second portion. The spacer is disposed in the trench and in contact with the sealant. The conductive material is disposed in the trench and encapsulates the spacer.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Chien-Feng CHAN
  • Publication number: 20190378817
    Abstract: A semiconductor package device comprises a substrate, a first electronic component, a first encapsulant, a second electronic component, and a first conductive trace. The substrate has a first surface. The first electronic component is on the first surface of the substrate. The first encapsulant is on the first surface of the substrate and covers the first electronic component. The second electronic component is on the first encapsulant. The first conductive trace is within the first encapsulant. The first conductive trace is electrically connected to the second electronic component.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Chia-Cheng LIU, Chien-Feng CHAN
  • Patent number: 10424545
    Abstract: The present disclosure provides for a semiconductor package device and a method for manufacturing the same. The semiconductor package device includes a substrate, a shielding wall and a package body. The substrate has a top surface. The shielding wall is disposed on the top surface. The shielding wall has a conductive main body and a plurality of protruding portions extending from the conductive main body. The package body encapsulates the shielding wall.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: JR-Wei Lin
  • Publication number: 20190115305
    Abstract: The present disclosure provides for a semiconductor package device and a method for manufacturing the same. The semiconductor package device includes a substrate, a shielding wall and a package body. The substrate has a top surface. The shielding wall is disposed on the top surface. The shielding wall has a conductive main body and a plurality of protruding portions extending from the conductive main body. The package body encapsulates the shielding wall.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 18, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: JR-Wei LIN