Patents by Inventor Jr-Yuan Jeng

Jr-Yuan Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8123965
    Abstract: An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: February 28, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Yu Hsu, Shyi-Ching Liau, Ra-Min Tain, Jr-Yuan Jeng
  • Patent number: 7586187
    Abstract: An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: September 8, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Yu Hsu, Shyi-Ching Liau, Ra-Min Tain, Jr-Yuan Jeng
  • Publication number: 20080264899
    Abstract: An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.
    Type: Application
    Filed: July 9, 2008
    Publication date: October 30, 2008
    Inventors: Yung-Yu HSU, Shyi-Ching Liau, Ra-Min Tain, Jr-Yuan Jeng
  • Publication number: 20070228549
    Abstract: An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.
    Type: Application
    Filed: June 23, 2006
    Publication date: October 4, 2007
    Inventors: Yung-Yu Hsu, Shyi- Liau, Ra-Min Tain, Jr-Yuan Jeng