Patents by Inventor Ju-Ai Ruan
Ju-Ai Ruan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9052507Abstract: A novel method of modulating the motion or displacement of function units in MEMS (micro-electro-mechanical-system) devices (or MEMS motion transducers) is described. This method generates small vertical displacement of one MEMS component (activation component) in the device and effectively translates that displacement into the displacement of another MEMS component (function unit) in the same device in an in-plan direction that is perpendicular to the direction of the vertical displacement of activation component. The activation component has a large surface area of electrostatic interaction with its interacting electrode, capable of generating large activation force at small voltages. Therefore this method makes it effective to modulate the motion or displacement of the function unit of MEMS motion transducers in an in-plan direction at low voltages. Specific designs of MEMS motion transducers employing this method are disclosed.Type: GrantFiled: February 12, 2013Date of Patent: June 9, 2015Inventor: Ju-Ai Ruan
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Patent number: 7995263Abstract: A spatial light modulator suitable for flat panel displays and methods of making the modulators are disclosed. The light modulator comprises a light separator, integrated circuits (IC), light switches (concurrently called light shutters), and optional color filters. The light separator is used to direct light uniformly illuminated on the incident surface (entrance surface) into individual pixels, and condenses the light within each pixel to a small fraction of pixel space on the viewing surface. ICs and light shutters are used to control color and light intensity at individual pixels. Several novel designs of the light modulator and light shutters are disclosed. Methods of building self-aligned structures for placing micro-spherical ball spacers for attaching protective screens to the light modulator is also disclosed.Type: GrantFiled: December 26, 2008Date of Patent: August 9, 2011Inventor: Ju-Ai Ruan
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Patent number: 7745335Abstract: A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.Type: GrantFiled: December 21, 2006Date of Patent: June 29, 2010Assignee: Texas Instruments IncorporatedInventors: Ju-Ai Ruan, Changming Jin, Sopa Chevacharoenkul, Satyavolu Papa Rao, Tae Seung Kim
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Patent number: 7732324Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).Type: GrantFiled: December 20, 2007Date of Patent: June 8, 2010Assignee: Texas Instruments IncorporatedInventors: Ju-Ai Ruan, Sameer K. Ajmera, Changming Jin, Anand J. Reddy, Tae S. Kim
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Patent number: 7727885Abstract: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.Type: GrantFiled: August 29, 2006Date of Patent: June 1, 2010Assignee: Texas Instruments IncorporatedInventors: Phillip Daniel Matz, Sopa Chevacharoenkul, Ching-Te Lin, Basab Chatterjee, Anand Reddy, Kenneth Joseph Newton, Ju-Ai Ruan
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Publication number: 20090160059Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: Texas Instruments IncorporatedInventors: Ju-Ai Ruan, Sameer K. Ajmera, Changming Jin, Anand J. Reddy, Tae S. Kim
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Publication number: 20080150131Abstract: A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Applicant: Texas Instruments IncorporatedInventors: Ju-Ai Ruan, Changming Jin, Sopa Chevacharoenkul, Satyavolu Papa Rao, Tae Seung Kim
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Publication number: 20080057711Abstract: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.Type: ApplicationFiled: August 29, 2006Publication date: March 6, 2008Inventors: Phillip Daniel Matz, Sopa Chevacharoenkul, Ching-Te Lin, Basab Chatterjee, Anand Reddy, Kenneth Joseph Newton, Ju-Ai Ruan
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Publication number: 20060194447Abstract: A method of manufacturing an etch stop layer 18, 20, 21 on a semiconductor wafer 2 and the etch stop layer 18, 20, 21 produced by the method. The method includes depositing a dielectric layer 18, 20, 21 and applying a plasma treatment to the semiconductor wafer 2. Also, an etch stop layer 18, 20, 21 on a semiconductor wafer 2 having a modified surface and an amine deficient bulk.Type: ApplicationFiled: May 12, 2006Publication date: August 31, 2006Applicant: Texas Instruments IncorporatedInventors: Ju-Ai Ruan, Qi-Zhong Hong, Zhijian Lu
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Publication number: 20060081965Abstract: A method of manufacturing an etch stop layer 18, 20, 21 on a semiconductor wafer 2 and the etch stop layer 18, 20, 21 produced by the method. The method includes depositing a dielectric layer 18, 20, 21 and applying a plasma treatment to the semiconductor wafer 2. Also, an etch stop layer 18, 20, 21 on a semiconductor wafer 2 having a modified surface and an amine deficient bulk.Type: ApplicationFiled: October 15, 2004Publication date: April 20, 2006Inventors: Ju-Ai Ruan, Qi-Zhong Hong, Zhijian Lu
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Publication number: 20050241672Abstract: A method comprises extracting impurities from one or more materials in a semiconductor device via treatment with a supercritical fluid (SCF). The SCF may comprise a solvent and one or more co-solvents. Solvents may comprise 1-hexanol, 1-propanol, 2-propanol, acetone, ammonia, argon, carbon dioxide, chlorotrifluoromethane, cyclohexane, dichlorodifluoromethane, ethane, ethyl alcohol, ethylene, methane, methanol, n-butane, n-hexane, nitrous oxide, n-pentane, propane, propylene, toluene, trichlorofluoromethane, trichloromethane, water, or combinations thereof.Type: ApplicationFiled: August 13, 2004Publication date: November 3, 2005Applicant: Texas Instruments IncorporatedInventors: Phillip Matz, Sameer Ajmera, Ju-Ai Ruan, Jinyoung Kim, Zhijian Lu, Laura Matz
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Patent number: 6790777Abstract: The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and establishing a first loading position in a first process chamber. The first and second substrates are consecutively inserted into the first process chamber and generally simultaneously processed, wherein the oxidized region is reduced by exposure to a first plasma. The first and second substrates are then consecutively removed and the first substrate is inserted into a second process chamber and subsequently processed. The second substrate is then inserted into the second process chamber and the first and second substrates are simultaneously processed. The first substrate is the removed, and the second substrate is processed again.Type: GrantFiled: November 6, 2002Date of Patent: September 14, 2004Assignee: Texas Instruments IncorporatedInventors: Glenn J. Tessmer, Ju-Ai Ruan, Mercer Lusk Brugler, Sarah Hartwig
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Publication number: 20040087149Abstract: The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and establishing a first loading position in a first process chamber. The first and second substrates are consecutively inserted into the first process chamber and generally simultaneously processed, wherein the oxidized region is reduced by exposure to a first plasma. The first and second substrates are then consecutively removed and the first substrate is inserted into a second process chamber and subsequently processed. The second substrate is then inserted into the second process chamber and the first and second substrates are simultaneously processed. The first substrate is the removed, and the second substrate is processed again.Type: ApplicationFiled: November 6, 2002Publication date: May 6, 2004Inventors: Glenn J. Tessmer, Ju-Ai Ruan, Mercer Lusk Brugler, Sarah Hartwig
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Patent number: 6686283Abstract: A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.Type: GrantFiled: February 4, 2000Date of Patent: February 3, 2004Assignee: Texas Instruments IncorporatedInventors: Shawn T. Walsh, John E. Campbell, Somit Joshi, James B. Friedmann, Michael J. McGranaghan, Janice D. Makos, Arun Sivasothy, Troy A. Yocum, Jaideep Mavoori, Wayne A. Bather, Joe G. Tran, Ju-Ai Ruan, Michelle L. Hartsell, Gregory B. Shinn
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Publication number: 20030162403Abstract: A method for reducing/eliminating plasma damage in semiconductor wafer (100) processing is introduced. The method is applicable to most semiconductor processes that involves the use of plasma, and does not affect process results other than reducing antenna damage. After exposing the wafer (100) to plasma excited gases (108), a cooling/idle step is added to allow the plasma to discharge prior to removing the wafer (100) from the process chamber (104).Type: ApplicationFiled: February 28, 2002Publication date: August 28, 2003Inventor: Ju-Ai Ruan