Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer, a test structure, and a photoresist pattern. The semiconductor wafer has a substrate with die areas separated by a scribe line area. The test structure disposed in the scribe line area includes first and second transistor test units. The photoresist pattern is arranged between the first and second transistor test units. The first gate structures of the first and second transistor test units are electrically connected to each other. The second gate structures of the first and second transistor test units are electrically connected to each other. A first drain region of the first transistor test unit is electrically connected to a first source region of the second transistor test unit. A second drain region of the first transistor test unit is electrically connected to a second source region of the second transistor test unit.

Abstract: A semiconductor package structure includes a first substrate, a capacitor structure, a plurality of first conductive connectors, and a plurality of second conductive connectors. The capacitor structure includes a semiconductor substrate, a first capacitor, and a second capacitor. The semiconductor substrate has a first surface and a second surface opposite the first surface. The first capacitor is disposed on the first surface of the semiconductor substrate. The second capacitor is disposed on the second surface of the semiconductor substrate. The first conductive connectors are disposed over the capacitor structure and electrically coupled to the first capacitor. The second conductive connectors are disposed below the capacitor structure and electrically coupled to the second capacitor.

Abstract: A semiconductor structure includes a semiconductor substrate, a first capacitor, a first conductive via, a second conductive via, a second capacitor, a first conductive pad, and a second conductive pad. The first capacitor is disposed over the semiconductor substrate. The first conductive via is disposed over the first capacitor. The second conductive via is bonded to the first conductive via. The second capacitor is disposed over the second conductive via. The first conductive pad and the second conductive pad are disposed over the second capacitor and are electrically coupled to the first capacitor and the second capacitor.

Abstract: A semiconductor package structure includes a first redistribution layer, a capacitor structure, and a second redistribution layer. The capacitor structure is disposed over the first redistribution layer and includes a semiconductor substrate, a first capacitor cell, a second capacitor cell, and a through via. The first capacitor cell and the second capacitor cell are disposed over the semiconductor substrate and separated by a first scribe line region. The through via is disposed in the first scribe line region. The second redistribution layer is disposed over the capacitor structure and is electrically coupled to the first redistribution layer through the through via.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer and a test structure. The semiconductor wafer has a substrate having a scribe line area and die areas. The die areas are separated by the scribe line area. The test structure is disposed in the scribe line area. The test structure includes an isolation feature, a first transistor test device, a second transistor test device. The isolation feature is located in the substrate. The first transistor test device and the second transistor test device are disposed on opposite sides of the isolation feature. Channels of the first transistor test device and the second transistor test device have the same conductivity type. A first gate electrode of the first transistor test device and a second gate electrode of the second transistor test device have opposite conductivity types.

Abstract: A semiconductor package structure includes a substrate, a composite interposer, and a semiconductor die. The composite interposer is disposed over the substrate and includes a first interposer substrate and a second interposer substrate. The first interposer substrate includes a first conductive via and a first dielectric layer. The second interposer substrate is disposed over the first interposer substrate and includes a second conductive via and a second dielectric layer. The second conductive via is bonded to the first conductive via, and the second dielectric layer is bonded to the first dielectric layer. The semiconductor die is disposed over the composite interposer and is electrically coupled to the first conductive via and the second conductive via.

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.

Abstract: A method for fabricating semiconductor package structure is disclosed. The method includes: providing a wafer having a front side and a backside; forming a plurality of through-silicon vias (TSVs) in the wafer and a plurality of metal interconnections on the TSVs, in which the metal interconnections are exposed from the front side of the wafer; performing a monitoring step to screen for TSV failures from the backside of the wafer; and bonding the wafer to a substrate.

Abstract: A method of manufacturing through-silicon-via (TSV) including the steps of sequentially forming a liner layer and a metal layer in a TSV hole, performing a chemical mechanical polishing process to remove the metal layer on the substrate so that the remaining metal layer in the TSV hole becomes a TSV, and forming a cap layer on the substrate without performing a NH3 treatment.

Abstract: A method of fabricating a through silicon via structure includes the following steps. At first, a substrate is provided, and a dielectric layer is formed on the substrate. Subsequently, at least one first opening is formed in the dielectric layer, and the substrate exposed by the first opening is partially removed to form at least one via opening. A conductive material layer is then formed to fill the via opening and the first opening, and the conductive material layer is planarized.

Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a gate and a source/drain region thereon; forming a Ni—Pt layer on surface of the gate and the source/drain region; performing a first rapid thermal process to react a portion of the Ni—Pt layer into a silicide layer; removing un-reacted nickel from the first rapid thermal process; removing un-reacted platinum from the first rapid thermal process; performing a second rapid thermal process for lowering the resistance of the silicide layer; and covering a contact etch stop layer (CESL) on the silicide layer after the second rapid thermal process.