Patents by Inventor Ju-Beom Lee

Ju-Beom Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Optical phased array chip using MEMS switch and manufacturing method thereof
    Patent number: 11640030
    Abstract: Disclosed are an optical phased array chip and a method of manufacturing the same. The optical phased array chip includes a plurality of optical switches and a plurality of optical phased arrays implemented on a single integrated circuit, wherein the single integrated circuit includes a silicon substrate, a lower layer formed on an upper portion of the silicon substrate, a silicon layer formed on an upper portion of the lower layer, a first upper layer, a second upper layer and a third upper layer sequentially arranged on the silicon layer, and an electrode that penetrates through the first upper layer while being grounded to the silicon layer and is formed on an upper portion of the first upper layer.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: May 2, 2023
    Assignees: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyo-Hoon Park, Jong-Bum You, Dong-Eun Yoo, Ju-Beom Lee, In Ki Kim, Tae Joon Seok, Geumbong Kang, Hyeonho Yoon, Nam-Hyun Kwon
  • OPTICAL PHASED ARRAY CHIP USING MEMS SWITCH AND MANUFACTURING METHOD THEREOF
    Publication number: 20220229233
    Abstract: Disclosed are an optical phased array chip and a method of manufacturing the same. The optical phased array chip includes a plurality of optical switches and a plurality of optical phased arrays implemented on a single integrated circuit, wherein the single integrated circuit includes a silicon substrate, a lower layer formed on an upper portion of the silicon substrate, a silicon layer formed on an upper portion of the lower layer, a first upper layer, a second upper layer and a third upper layer sequentially arranged on the silicon layer, and an electrode that penetrates through the first upper layer while being grounded to the silicon layer and is formed on an upper portion of the first upper layer.
    Type: Application
    Filed: January 14, 2022
    Publication date: July 21, 2022
    Applicants: Korea Advanced Institute of Science and Technology, Gwangju Institute of Science and Technology
    Inventors: Hyo-Hoon Park, Jong-Bum You, Dong-Eun Yoo, Ju-Beom Lee, In Ki Kim, Tae Joon Seok, Geumbong Kang, Hyeonho Yoon, Nam-Hyun Kwon