Patents by Inventor Ju-Beom Yi

Ju-Beom Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8357576
    Abstract: A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chong-Kwang Chang, Sung-Hon Chi, Hong-Jae Shin, Yong-Jin Chung, Young-Mook Oh, Ju-Beom Yi
  • Publication number: 20110256700
    Abstract: A method of fabricating a semiconductor device capable of simplifying a fabrication process is provided.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 20, 2011
    Inventors: Chong-Kwang Chang, Sung-Hon Chi, Young-Mook Oh, Ju-Beom Yi
  • Publication number: 20110201202
    Abstract: A method of forming fine patterns of a semiconductor device, the method including providing a patternable layer; forming a plurality of first photoresist layer patterns on the patternable layer; forming an interfacial layer on the patternable layer and the plurality of first photoresist layer patterns; forming a planarization layer on the interfacial layer; forming a plurality of second photoresist layer patterns on the planarization layer; forming a plurality of planarization layer patterns using the plurality of second photoresist layer patterns; and forming a plurality of layer patterns using the plurality of planarization layer patterns and the plurality of first photoresist layer patterns.
    Type: Application
    Filed: January 14, 2011
    Publication date: August 18, 2011
    Inventors: Chong-Kwang CHANG, Young-Mook OH, Seo-Woo NAM, Woo-Cheol JEON, Ju-Beom YI, Myung-Joo LEE
  • Publication number: 20110195550
    Abstract: A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.
    Type: Application
    Filed: January 14, 2011
    Publication date: August 11, 2011
    Inventors: Chong-Kwang CHANG, Sung-Hon Chi, Hong-Jae Shin, Yong-Jin Chung, Young-Mook Oh, Ju-Beom Yi