Abstract: A semiconductor package includes a substrate, a semiconductor layer on the substrate, a wiring structure on the semiconductor layer, a connection pad on and connected to the wiring structure, a test pad on and connected to the wiring structure, the test and connection pads being horizontally spaced from each other, a first liner film on the wiring structure and having a first bonding pad trench, a second liner film on the first liner film and having a second bonding pad trench, a first bonding pad including a barrier layer in contact with the first liner film and a metal layer on the barrier layer, and a second bonding pad filling an inner portion of the second bonding pad trench and in contact with the second liner film, wherein the second liner film integrally covers upper surfaces of the barrier layer and metal layer.

Abstract: A semiconductor device includes a first semiconductor chip having a first pad structure and a second semiconductor chip having a second pad structure. The first pad structure and the second pad structure are bonded to each other in a first direction. The first pad structure includes a first filling conductive film and a second filling conductive film. The first filling conductive film includes a first portion that overlaps the second filling conductive film in the first direction, and a second portion that overlaps the second filling conductive film in a second direction intersecting the first direction. A first height of the first portion in the first direction is greater than a thickness of the second portion in the second direction, and an electrical conductivity of the second filling conductive film is greater than the electrical conductivity of the first filling conductive film.

Abstract: A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.

Abstract: A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

Abstract: A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

Abstract: A semiconductor package includes a substrate, a semiconductor layer on the substrate, a wiring structure on the semiconductor layer, a connection pad on and connected to the wiring structure, a test pad on and connected to the wiring structure, the test and connection pads being horizontally spaced from each other, a first liner film on the wiring structure and having a first bonding pad trench, a second liner film on the first liner film and having a second bonding pad trench, a first bonding pad including a barrier layer in contact with the first liner film and a metal layer on the barrier layer, and a second bonding pad filling an inner portion of the second bonding pad trench and in contact with the second liner film, wherein the second liner film integrally covers upper surfaces of the barrier layer and metal layer.

Abstract: A semiconductor device including a substrate, a wiring pattern in the substrate, a passivation layer on the substrate, the passivation layer and the substrate including a first recess penetrating a part of each of the passivation layer and the substrate and extending toward the wiring pattern, a post connected to the wiring pattern and including a first portion within the first recess and a second portion on the first portion and protruding from a top surface of the passivation layer, a signal bump including a seed layer on the post, a lower bump on the seed layer, and an upper bump on the lower bump, and a heat transfer bump apart from the signal bump, electrically insulated from the wiring pattern, and including another seed layer on the passivation layer, another lower bump on the another seed layer, and another upper bump on the another lower bump may be provided.

Abstract: A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.

Abstract: A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.

Abstract: A semiconductor device including a substrate including a first conductive pad on a first surface thereof, at least one first bump structure on the first conductive pad, the first bump structure including a first connecting member and a first delamination prevention layer, the first delamination prevention layer on the first connecting member and having a greater hardness than the first connecting member, and a first encapsulant above the first surface of the substrate and surrounding the first bump structure may be provided.

Abstract: A nanostructure semiconductor light emitting device includes a base layer, an insulating layer and a plurality of light emitting nanostructures. The base layer is formed of a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base layer are exposed. Each of the light emitting nanostructures is disposed on the exposed regions of the base layer and includes nanocore formed of a first conductivity type semiconductor, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on side surfaces of the nanocore. Upper surfaces of the light emitting nanostructures are non-planar and contain portions free of the second conductivity-type semiconductor layer in order to prevent light emissions during device driving.

Abstract: A semiconductor light emitting device is provided and includes a protective element including a first lower conductivity-type semiconductor layer and a second lower conductivity-type semiconductor layer. First and second lower electrodes are connected to the first lower conductivity-type semiconductor layer and the second lower conductivity-type semiconductor layer, respectively. A light emitting structure includes a first upper conductivity-type semiconductor layer, an active layer, and a second upper conductivity-type semiconductor layer sequentially formed on the protective element. First and second upper electrodes are connected to the first upper conductivity-type semiconductor layer and the second upper conductivity-type semiconductor layer, respectively.

Abstract: A nanostructure semiconductor light emitting device includes a base layer, an insulating layer and a plurality of light emitting nanostructures. The base layer is formed of a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base layer are exposed. Each of the light emitting nanostructures is disposed on the exposed regions of the base layer and includes nanocore formed of a first conductivity type semiconductor, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on side surfaces of the nanocore. Upper surfaces of the light emitting nanostructures are non-planar and contain portions free of the second conductivity-type semiconductor layer in order to prevent light emissions during device driving.

Abstract: A method of manufacturing a semiconductor light emitting device includes preparing a light emitting structure including first and second conductivity type semiconductor layers and an active layer interposed therebetween, forming a plurality of seeds on at least one surface of the light emitting structure, and forming a plurality of dome-shaped protrusions by forming optical waveguide groups from the plurality of respective seeds and combining the optical waveguide groups.

Abstract: A semiconductor light emitting device is provided and includes a protective element including a first lower conductivity-type semiconductor layer and a second lower conductivity-type semiconductor layer. First and second lower electrodes are connected to the first lower conductivity-type semiconductor layer and the second lower conductivity-type semiconductor layer, respectively. A light emitting structure includes a first upper conductivity-type semiconductor layer, an active layer, and a second upper conductivity-type semiconductor layer sequentially formed on the protective element. First and second upper electrodes are connected to the first upper conductivity-type semiconductor layer and the second upper conductivity-type semiconductor layer, respectively.