Abstract: A semiconductor device includes a first transistor located in a first region and a second transistor located in a second region. The first transistor includes first and second channel members vertically stacked above the substrate, and a first gate dielectric layer having a first portion wrapping around the first channel member and a second portion wrapping around the second channel member. The second transistor includes third and fourth channel member vertically stacked above the substrate and a second gate dielectric layer having a first portion wrapping around the third channel member and a second portion wrapping around the fourth channel member. The first and second channel members are thicker than the third and fourth channel members. A vertical distance between the first and second portions of the first gate dielectric layer is larger than a vertical distance between the first and second portions of the second gate dielectric layer.

Abstract: A detection device with a calibration function is configured to detect an object. The detection device includes an antenna element, a transmission line, a detection circuit, and a processor. The transmission line is coupled to the antenna element. The detection circuit is coupled to the transmission line. The detection circuit performs a detection process, so as to obtain an estimated distance between the antenna element and the object. The processor is coupled to the detection circuit. The processor calculates the calibrated distance by subtracting the error distance from the estimated distance.

Abstract: The invention relates to Proprotein Convertase Subtilisin Kexin type 9 (PCSK9) antagonists, such as antibodies and fragments, as well as methods, uses and combinations.

Abstract: An electronic package and a manufacturing method thereof are provided, in which the electronic package includes: a first circuit module including a dielectric material, a first circuit layer, a second circuit layer, a third circuit layer and a fourth circuit layer; a first electronic element embedded in the first circuit module and electrically connected to the fourth circuit layer; a second circuit module electrically connected to the first circuit layer; and a second electronic element located between the first circuit layer and the second circuit module. Accordingly, the overall thickness of the electronic package can be greatly reduced to save space; the heat dissipation effect of the electronic elements can also be improved to extend their service life; and the manufacturing process can also be effectively simplified to improve yield and production rate and reduce manufacturing costs.

Abstract: An apparatus for quick detection of a blood pressure level is described. The apparatus comprises a module, a device and a network processor. The module is for capturing data of a heart sound. The device is for transforming the data into a plurality of time-frequency spectrograms having a plurality of image features. The network processor is trained to analyze the image features of the time-frequency spectrograms, for giving the blood pressure level. The network processor is equipped with a convolutional neural network trained to analyze the image features of the time-frequency spectrograms, by focusing on a second heart sound, for detecting the hypertension. The network processor is also trained to identify the time-frequency spectrograms within a frequency band, to distinguish the long-term hypertension and the exercise-induced transient hypertension.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

Abstract: Provided is a package substrate including a dielectric layer having a first surface and a second surface opposite to the first surface; an insulating layer formed on the first surface of the dielectric layer and having a plurality of grooves; a first circuit layer formed in the plurality of grooves and flush with the insulating layer; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer and electrically connected to the first circuit layer and the second circuit layer. The present disclosure further provides a method of manufacturing the package substrate.

Abstract: Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.

Abstract: A method of manufacturing a composite metal foil includes providing a first metal layer and forming a second metal layer on a surface of the first metal layer through electroplating. The first metal layer is copper foil, nickel foil, stainless steel foil, or a combination thereof. A contact angle of a surface of the second metal layer to liquid lithium metal is lower than 90 degrees.

Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

Abstract: An image processing method and apparatus is provided that includes receiving two consecutive image frames captured live by an image capture apparatus, each of the two image frames including a subject wearing a head mount display device, generate a first bounding box surrounding the head mount display device using orientation information obtained from the head mount display, generate a second bounding box surrounding the head mount display using an object detection model trained to identify the head mount display, calculate a difference indicator by comparing differences, on a pixel by pixel basis between the generated first and second bounding boxes, select the first bounding box when it is determined that the difference indicator exceeds a predetermined threshold, provide coordinates representing the first bounding box to identify a region within the images to be replaced by a region of a precaptured image that is occluded by the head mount display device.

Abstract: An image resolution adjustment method and an electronic device are disclosed. The method includes: executing a target application to obtain a target image with a first resolution based on a first frame rate; and during an execution of the target application, selecting a target memory from a plurality of buffer memories according to a usage rate of each of the buffer memories; processing the target image by an image processing model and the target memory to adjust a resolution of the target image from the first resolution to a second resolution, where the second resolution is higher than the first resolution; and controlling a display interface to present the target image with the second resolution based on the first frame rate.

Abstract: An instruction query method, a computer program product, and an associated query system are provided. A software program is stored in the computer program product, and the software program performs the instruction query method. The instruction query method includes the following steps. Firstly, a language translator translates a non-English query string into an English query string according to a language identification code. Then, a prompt tuning module transforms the English query string into an English interactive prompt string according to at least one high-relevance token vector. The at least one high-relevance token vector relates to the operating instructions of an electronic device. Afterward, the language translator translates an English reply string into a non-English reply string according to the language identification code. The English reply string is generated based on inferences made from the English interactive prompt string.

Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

Abstract: A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube.

Abstract: An electronic device with dynamic lighting effect and a method for generating dynamic lighting effect are provided. The method for generating dynamic lighting effect includes the following steps. A lighting effect tracking frame is provided according to an eye position of a user, a dynamic lighting effect frame is received, or a predefined lighting effect frame is stored. The lighting effect tracking frame, the dynamic lighting effect frame or the predefined lighting effect frame is obtained. A size adjustment procedure is performed on the lighting effect tracking frame, the dynamic lighting effect frame or the predefined lighting effect frame to obtain a lighting effect control map. The dynamic lighting effect device is controlled according to the lighting effect control map to generate the dynamic lighting effect.

Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.

Abstract: A chimeric signal peptide for protein expression includes an N-region, a hydrophobic region, and a C-region, wherein the N-region and the C-region are from a same signal peptide of a first protein and the hydrophobic region is from a signal peptide of a second protein, wherein the first protein is different from the second protein. The first and second protein are independently selected from the group consisting of BM40, IL2, HA, Insulin, CD33, IFNA2, IgGK leader, AZU, and SEAP.