Patents by Inventor Ju-Cheol Shin

Ju-Cheol Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7135407
    Abstract: In a method of manufacturing a semiconductor device, a tungsten layer pattern having an oxidized surface is formed on a substrate. A source gas including silicon is provided to the oxidized surface of the tungsten layer pattern to form a protecting layer on the oxidized surface of the tungsten layer pattern. The protecting layer prevents an abnormal growth of oxide contained in the oxidized surface. The protecting layer prevents a whisker from growing from the oxidized surface of the tungsten layer pattern.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: November 14, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Cheol Shin, Hong-Mi Park, In-Sun Park, Hyeon-Deok Lee
  • Patent number: 7122468
    Abstract: An integrated circuit includes a substrate and a first insulating layer on the substrate that includes a first hole including a floor and a sidewall. A first conductive contact extends conformally on the sidewall and floor to define a groove in the first hole. A second insulating layer is provided on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is provided in the second hole and in the groove. These integrated circuits are fabricated by forming a first insulating layer on a substrate that includes a first hole including a floor and a sidewall. A first conductive contact is conformally formed on the sidewall and floor to define a groove in the first hole. A second insulating layer is formed on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is formed in the second hole and in the groove.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: October 17, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Cheol Shin, Hyeon-Deok Lee, Hong-Mi Park, In-Sun Park
  • Patent number: 6905960
    Abstract: In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: June 14, 2005
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hong-Mi Park, Jong-Sik Chun, Hyeon-Deok Lee, In-Sun Park, Jong-Myeong Lee, Ju-Cheol Shin
  • Publication number: 20050121755
    Abstract: An integrated circuit includes a substrate and a first insulating layer on the substrate that includes a first hole including a floor and a sidewall. A first conductive contact extends conformally on the sidewall and floor to define a groove in the first hole. A second insulating layer is provided on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is provided in the second hole and in the groove. These integrated circuits are fabricated by forming a first insulating layer on a substrate that includes a first hole including a floor and a sidewall. A first conductive contact is conformally formed on the sidewall and floor to define a groove in the first hole. A second insulating layer is formed on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is formed in the second hole and in the groove.
    Type: Application
    Filed: January 20, 2005
    Publication date: June 9, 2005
    Inventors: Ju-Cheol Shin, Hyeon-Deok Lee, Hong-Mi Park, In-Sun Park
  • Publication number: 20040259344
    Abstract: A preliminary metal layer having a first thickness is formed on a substrate. A surface of the preliminary metal layer having uneven portions is etched to remove the uneven portions and to form a metal layer having an improved surface morphology. Therefore, shorts caused by the surface morphology of a metal layer occur less frequently and the semiconductor fabricating yield improves.
    Type: Application
    Filed: April 22, 2004
    Publication date: December 23, 2004
    Inventors: Dong-Kyun Park, Ju-Cheol Shin, Hyeon-Deok Lee, In-Sun Park, Hyun-Seok Lim
  • Publication number: 20040198041
    Abstract: In a method of manufacturing a semiconductor device, a tungsten layer pattern having an oxidized surface is formed on a substrate. A source gas including silicon is provided to the oxidized surface of the tungsten layer pattern to form a protecting layer on the oxidized surface of the tungsten layer pattern. The protecting layer prevents an abnormal growth of oxide contained in the oxidized surface. The protecting layer prevents a whisker from growing from the oxidized surface of the tungsten layer pattern.
    Type: Application
    Filed: April 1, 2004
    Publication date: October 7, 2004
    Inventors: Ju-Cheol Shin, Hong-Mi Park, In-Sun Park, Hyeon-Deok Lee
  • Patent number: 6797575
    Abstract: A method for preventing void formation in a polycide structure includes sequentially depositing a gate oxide film, a polysilicon film doped with impurities, a seed film having a sufficient amount of silicon for reacting with an overlaying tungsten layer, a tungsten silicide precursor layer; and an etch mask made of an insulating material on a semiconductor substrate; performing a patterned etching using the etch mask; and heat-treating the resulting structure in an oxygen atmosphere at an elevated temperature and pressure to form a polycide structure wherein void formation is prevented. Since the seed film has a sufficient amount of amorphous silicon for reacting to the tungsten, migration of silicon atoms to the interfacial surface between the polysilicon film and the tungsten silicide precursor layer is prevented, thereby preventing the formation of voids in the polysilicon film.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: September 28, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Cheon Kim, In-Sun Park, Ju-Cheol Shin
  • Patent number: 6774029
    Abstract: Disclosed are methods for forming a conductive film or a conductive pattern on a semiconductor substrate, including nitrifying a semiconductor substrate on which a tungsten film having a partially oxidized surface is formed to form a tungsten nitride film on the surface of the tungsten film, oxidizing the surface of the tungsten film having the tungsten nitride film to change the tungsten nitride film into a tungsten oxy-nitride film, and removing the tungsten oxy-nitride film and any residue generated by a reaction of tungsten from the surface of the tungsten film to form a tungsten film. Complete removal of residues generated by a reaction of tungsten from the surface of the tungsten film is made possible. Therefore, resistance of the tungsten film may be reduced, and failures generated by reacted residues formed on tungsten films may be prevented.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: August 10, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Cheol Shin, Hyeon-Deok Lee, Hong-mi Park, In-Sun Park
  • Publication number: 20040067607
    Abstract: The present invention relates to metal interconnections for bit lines having a low resistance and an advanced morphology and a method of forming the same including: forming an inter-layer insulation film on a semiconductor substrate, the inter-layer insulation film containing a contact hole for the bit line; forming a plug within the contact hole; forming a barrier metal defined on the plug; and forming a bit line on the inter-layer insulation film.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 8, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Cheol Shin, In-Sun Park
  • Publication number: 20040053491
    Abstract: In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.
    Type: Application
    Filed: September 9, 2003
    Publication date: March 18, 2004
    Inventors: Hong-Mi Park, Jong-Sik Chun, Hyeon-Deok Lee, In-Sun Park, Jong-Myeong Lee, Ju-Cheol Shin
  • Publication number: 20040038530
    Abstract: Disclosed are methods for forming a conductive film or a conductive pattern on a semiconductor substrate, including nitrifying a semiconductor substrate on which a tungsten film having a partially oxidized surface is formed to form a tungsten nitride film on the surface of the tungsten film, oxidizing the surface of the tungsten film having the tungsten nitride film to change the tungsten nitride film into a tungsten oxy-nitride film, and removing the tungsten oxy-nitride film and any residue generated by a reaction of tungsten from the surface of the tungsten film to form a tungsten film. Complete removal of residues generated by a reaction of tungsten from the surface of the tungsten film is made possible. Therefore, resistance of the tungsten film may be reduced, and failures generated by reacted residues formed on tungsten films may be prevented.
    Type: Application
    Filed: July 14, 2003
    Publication date: February 26, 2004
    Inventors: Ju-Cheol Shin, Hyeon-Deok Lee, Hong-Mi Park, In-Sun Park
  • Publication number: 20040000717
    Abstract: An integrated circuit includes a substrate and a first insulating layer on the substrate that includes a first hole including a floor and a sidewall. A first conductive contact extends conformally on the sidewall and floor to define a groove in the first hole. A second insulating layer is provided on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is provided in the second hole and in the groove. These integrated circuits are fabricated by forming a first insulating layer on a substrate that includes a first hole including a floor and a sidewall. A first conductive contact is conformally formed on the sidewall and floor to define a groove in the first hole. A second insulating layer is formed on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is formed in the second hole and in the groove.
    Type: Application
    Filed: June 25, 2003
    Publication date: January 1, 2004
    Inventors: Ju-Cheol Shin, Hyeon-Deok Lee, Hong-Mi Park, In-Sun Park
  • Patent number: 6670268
    Abstract: The present invention relates to metal interconnections for bit lines having a low resistance and an advanced morphology and a method of forming the same including: forming an inter-layer insulation film on a semiconductor substrate, the inter-layer insulation film containing a contact hole for the bit line; forming a plug within the contact hole; forming a barrier metal defined on the plug; and forming a bit line on the inter-layer insulation film.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: December 30, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Cheol Shin, In-Sun Park
  • Publication number: 20030219536
    Abstract: A chemical vapor deposition (CVD) method for depositing a silicide and a CVD system for performing the same are disclosed. A silicide is deposited on a substrate. Residual gases remaining from the depositing step are purged out by flowing air including H2O (g), to substantially remove fumes caused by the residual gases. In the purge step, the cycle purge is carried out at the conditions similar to the flow of atmosphere, to substantially remove the fumes.
    Type: Application
    Filed: June 24, 2003
    Publication date: November 27, 2003
    Inventors: Ju-Cheol Shin, In-Sun Park, Young-Cheon Kim, Chul Whang-Bo, Hyeon-Deok Lee
  • Patent number: 6623798
    Abstract: A chemical vapor deposition (CVD) method for depositing a suicide and a CVD system for performing the same are disclosed. A silicide is deposited on a substrate. Residual gases remaining from the depositing step are purged out by flowing air including H2O (g), to substantially remove fumes caused by the residual gases. In the purge step, the cycle purge is carried out at the conditions similar to the flow of atmosphere, to substantially remove the fumes.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: September 23, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Cheol Shin, In-Sun Park, Young-Cheon Kim, Chul Whang-Bo, Hyeon-Deok Lee
  • Publication number: 20020197859
    Abstract: A method for preventing void formation in a polycide structure includes sequentially depositing a gate oxide film, a polysilicon film doped with impurities, a seed film having a sufficient amount of silicon for reacting with an overlaying tungsten layer, a tungsten silicide precursor layer; and an etch mask made of an insulating material on a semiconductor substrate; performing a patterned etching using the etch mask; and heat-treating the resulting structure in an oxygen atmosphere at an elevated temperature and pressure to form a polycide structure wherein void formation is prevented. Since the seed film has a sufficient amount of amorphous silicon for reacting to the tungsten, migration of silicon atoms to the interfacial surface between the polysilicon film and the tungsten silicide precursor layer is prevented, thereby preventing the formation of voids in the polysilicon film.
    Type: Application
    Filed: March 20, 2002
    Publication date: December 26, 2002
    Inventors: Young-Cheon Kim, In-Sun Park, Ju-Cheol Shin
  • Publication number: 20020173129
    Abstract: The present invention relates to metal interconnections for bit lines having a low resistance and an advanced morphology and a method of forming the same including: forming an inter-layer insulation film on a semiconductor substrate, the inter-layer insulation film containing a contact hole for the bit line; forming a plug within the contact hole; forming a barrier metal defined on the plug; and forming a bit line on the inter-layer insulation film.
    Type: Application
    Filed: April 30, 2002
    Publication date: November 21, 2002
    Inventors: Ju-Cheol Shin, In-Sun Park
  • Publication number: 20020014205
    Abstract: A chemical vapor deposition (CVD) method for depositing a suicide and a CVD system for performing the same are disclosed. A silicide is deposited on a substrate. Residual gases remaining from the depositing step are purged out by flowing air including H2O (g), to substantially remove fumes caused by the residual gases. In the purge step, the cycle purge is carried out at the conditions similar to the flow of atmosphere, to substantially remove the fumes.
    Type: Application
    Filed: June 21, 2001
    Publication date: February 7, 2002
    Inventors: Ju-Cheol Shin, In-Sun Park, Young-Cheon Kim, Chul Whang-Bo, Hyeon-Deok Lee