Patents by Inventor JU-CHIEH CHENG
JU-CHIEH CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240087644Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.Type: ApplicationFiled: August 29, 2023Publication date: March 14, 2024Applicant: Winbond Electronics Corp.Inventors: I-Hsien Tseng, Lung-Chi Cheng, Ju-Chieh Cheng, Jun-Yao Huang, Ping-Kun Wang
-
Publication number: 20230274782Abstract: A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.Type: ApplicationFiled: December 1, 2022Publication date: August 31, 2023Applicant: Winbond Electronics Corp.Inventors: Lung-Chi Cheng, Ying-Shan Kuo, Jun-Yao Huang, Ju-Chieh Cheng, Yu-Cheng Chuang
-
Patent number: 11437101Abstract: A resistive memory storage apparatus including a memory cell, a selecting transistor and a memory controller is provided. The memory cell outputs a writing current during a writing pulse width period. The selecting transistor is coupled to the memory cell. The memory controller is coupled to the selecting transistor and the memory cell. The memory controller is configured to apply a control voltage that gradually changes to a predetermined voltage level to a control end of the selecting transistor during a resistance transition phase of the writing pulse width period and set the control voltage to the predetermined voltage level during a filament stabilization phase after the resistance transition phase, so as to limit the writing current to a predetermined current value. In addition, an operating method for a resistive memory storage apparatus is also provided.Type: GrantFiled: April 8, 2021Date of Patent: September 6, 2022Assignee: Winbond Electronics Corp.Inventors: Lih-Wei Lin, Lung-Chi Cheng, Ju-Chieh Cheng, Ying-Shan Kuo
-
Patent number: 11289160Abstract: A data writing method is provided. According to the present application, the data writing method includes steps of receiving an expected data, performing a plurality of readings on a target storage unit to obtain a plurality of read data; determining whether the plurality of read data are the same as the expected data respectively to generate a plurality of comparison results; and performing a writing operation procedure on the target storage unit according to the plurality of comparison results and the expected data.Type: GrantFiled: October 9, 2020Date of Patent: March 29, 2022Assignee: WINBOND ELECTRONICS CORP.Inventors: Lih-Wei Lin, Ju-Chieh Cheng, Lung-Chi Cheng, Ying-Shan Kuo, Yu-An Chen
-
Publication number: 20210335421Abstract: A resistive memory storage apparatus including a memory cell, a selecting transistor and a memory controller is provided. The memory cell outputs a writing current during a writing pulse width period. The selecting transistor is coupled to the memory cell. The memory controller is coupled to the selecting transistor and the memory cell. The memory controller is configured to apply a control voltage that gradually changes to a predetermined voltage level to a control end of the selecting transistor during a resistance transition phase of the writing pulse width period and set the control voltage to the predetermined voltage level during a filament stabilization phase after the resistance transition phase, so as to limit the writing current to a predetermined current value. In addition, an operating method for a resistive memory storage apparatus is also provided.Type: ApplicationFiled: April 8, 2021Publication date: October 28, 2021Applicant: Winbond Electronics Corp.Inventors: Lih-Wei Lin, Lung-Chi Cheng, Ju-Chieh Cheng, Ying-Shan Kuo
-
Publication number: 20210210139Abstract: A data writing method is provided. According to the present application, the data writing method includes steps of receiving an expected data, performing a plurality of readings on a target storage unit to obtain a plurality of read data; determining whether the plurality of read data are the same as the expected data respectively to generate a plurality of comparison results; and performing a writing operation procedure on the target storage unit according to the plurality of comparison results and the expected data.Type: ApplicationFiled: October 9, 2020Publication date: July 8, 2021Applicant: Winbond Electronics Corp.Inventors: Lih-Wei LIN, Ju-Chieh CHENG, Lung-Chi CHENG, Ying-Shan KUO, Yu-An CHEN
-
Patent number: 10978149Abstract: A resistive memory apparatus and an adjusting method for write-in voltage thereof are provided. The adjusting method for write-in voltage includes: selecting an under test memory cell array in a resistive memory; performing N reset operations on a plurality of memory cells of the under test memory cell array according to a reset voltage, and performing N set operations on the memory cells of the under test memory cell array according to a set voltage, wherein n is an integer greater than 1; calculating a reset time variation rate of the reset operations and a set time variation rate of the set operations; and adjusting a voltage value of one of the set voltage and the reset voltage according to the reset time variation rate and the set time variation rate.Type: GrantFiled: May 12, 2020Date of Patent: April 13, 2021Assignee: Winbond Electronics Corp.Inventors: Ju-Chieh Cheng, Ying-Shan Kuo, Lih-Wei Lin, Lung-Chi Cheng
-
Patent number: 10643698Abstract: An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.Type: GrantFiled: August 15, 2018Date of Patent: May 5, 2020Assignee: Windbond Electronics Corp.Inventors: Lih-Wei Lin, Ju-Chieh Cheng, Tsung-Huan Tsai, I-Hsien Tseng
-
Patent number: 10636507Abstract: A memory-testing method is adapted in a memory circuit including a first block and a second block including a plurality of row addresses and column addresses. The memory-testing method includes: selecting one of the row addresses and one of the column addresses as a testing row and a testing column according to selection logic; selecting sampled column addresses of the testing row and sampled row addresses of the testing column according to a sampling process; executing the read operation on the sampled column addresses of the testing row and the sampled row addresses of the testing column in the first block; determining whether the read fail rate of the first block exceeds a predetermined ratio; and marking the first block as an input/output fail when the read fail rate exceeds the predetermined ratio.Type: GrantFiled: June 8, 2018Date of Patent: April 28, 2020Assignee: WINBOND ELECTRONICS CORP.Inventors: Lih-Wei Lin, Tsung-Huan Tsai, Ju-Chieh Cheng
-
Publication number: 20200027507Abstract: An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.Type: ApplicationFiled: August 15, 2018Publication date: January 23, 2020Applicant: Winbond Electronics Corp.Inventors: Lih-Wei Lin, Ju-Chieh Cheng, Tsung-Huan Tsai, I-Hsien Tseng
-
Publication number: 20190378586Abstract: A memory-testing method is adapted in a memory circuit including a first block and a second block including a plurality of row addresses and column addresses. The memory-testing method includes: selecting one of the row addresses and one of the column addresses as a testing row and a testing column according to selection logic; selecting sampled column addresses of the testing row and sampled row addresses of the testing column according to a sampling process; executing the read operation on the sampled column addresses of the testing row and the sampled row addresses of the testing column in the first block; determining whether the read fail rate of the first block exceeds a predetermined ratio; and marking the first block as an input/output fail when the read fail rate exceeds the predetermined ratio.Type: ApplicationFiled: June 8, 2018Publication date: December 12, 2019Inventors: Lih-Wei LIN, Tsung-Huan TSAI, Ju-Chieh CHENG
-
Patent number: 10490275Abstract: A writing method of a resistive memory storage apparatus is provided. The writing method includes: applying a first set voltage on a memory cell, and acquiring a first reading current of the memory cell; applying a first disturbance voltage on the memory cell, and acquiring a second reading current of the memory cell; and determining to apply a second set voltage or a second disturbance voltage on the memory cell according to a magnitude relationship between the first reading current and the second reading current. An absolute value of the first disturbance voltage is smaller than an absolute value of a reset voltage, and an absolute value of the second disturbance voltage is smaller than an absolute value of the second set voltage. In addition, a resistive memory storage apparatus is also provided.Type: GrantFiled: July 30, 2018Date of Patent: November 26, 2019Assignee: Winbond Electronics Corp.Inventors: Lih-Wei Lin, Ju-Chieh Cheng, Tsung-Huan Tsai, I-Hsien Tseng
-
Publication number: 20190057738Abstract: A writing method of a resistive memory storage apparatus is provided. The writing method includes: applying a first set voltage on a memory cell, and acquiring a first reading current of the memory cell; applying a first disturbance voltage on the memory cell, and acquiring a second reading current of the memory cell; and determining to apply a second set voltage or a second disturbance voltage on the memory cell according to a magnitude relationship between the first reading current and the second reading current. An absolute value of the first disturbance voltage is smaller than an absolute value of a reset voltage, and an absolute value of the second disturbance voltage is smaller than an absolute value of the second set voltage. In addition, a resistive memory storage apparatus is also provided.Type: ApplicationFiled: July 30, 2018Publication date: February 21, 2019Applicant: Winbond Electronics Corp.Inventors: Lih-Wei Lin, Ju-Chieh Cheng, Tsung-Huan Tsai, I-Hsien Tseng
-
Patent number: 9627059Abstract: A resistive memory and a data writing method for a resistive memory cell thereof are provided. The method includes: receiving and decoding a column address signal for generating a decoded result, and providing a word line voltage to a word line of the resistive memory cell; providing a constant current to one of a bit line and a source line of the resistive memory cell, and coupling a reference ground voltage to another one of the bit line and the source line of the resistive memory cell.Type: GrantFiled: December 22, 2015Date of Patent: April 18, 2017Assignee: Winbond Electronics Corp.Inventors: Lih-Wei Lin, I-Hsien Tseng, Ju-Chieh Cheng, Chia-Hung Lin, Tsung-Huan Tsai, Po-Wei Huang
-
Patent number: 9620208Abstract: A memory-programming device includes a voltage generator, a resistive random-access memory, a current detector, and a controller. The voltage generator is configured to generate a program voltage. The resistive random-access memory receives the program voltage to generate a program current. The current detector detects the program current. The controller executes a program procedure. The program procedure includes: gradually ramping up the program voltage by the voltage generator and detecting the program current by the current detector; discovering the maximum of the program current to be a reference current; continuing to ramp up the program voltage by the voltage generator and determining whether the program current detected by the current detector is not less than the reference current; controlling the voltage generator to stop generating the program voltage when the program current is not less than the reference current.Type: GrantFiled: June 23, 2016Date of Patent: April 11, 2017Assignee: Winbond Electronics Corp.Inventors: Lih-Wei Lin, Tsung-Huan Tsai, Chia-Hung Lin, I-Hsien Tseng, Ju-Chieh Cheng
-
Publication number: 20170011798Abstract: A memory-programming device includes a voltage generator, a resistive random-access memory, a current detector, and a controller. The voltage generator is configured to generate a program voltage. The resistive random-access memory receives the program voltage to generate a program current. The current detector detects the program current. The controller executes a program procedure. The program procedure includes: gradually ramping up the program voltage by the voltage generator and detecting the program current by the current detector; discovering the maximum of the program current to be a reference current; continuing to ramp up the program voltage by the voltage generator and determining whether the program current detected by the current detector is not less than the reference current; controlling the voltage generator to stop generating the program voltage when the program current is not less than the reference current.Type: ApplicationFiled: June 23, 2016Publication date: January 12, 2017Inventors: Lih-Wei LIN, Tsung-Huan TSAI, Chia-Hung LIN, I-Hsien TSENG, Ju-Chieh CHENG
-
Patent number: 9543010Abstract: A measurement system including a testing machine and a resistive memory is provided. The resistive memory includes a first storage cell. The first storage cell includes a transistor and a variable resistor. During a specific period, the testing machine provides a write voltage to change the state of the variable resistor. During a maintaining period, the testing machine maintains the level of the write voltage and measures the current passing through the variable resistor. When the current passing through the variable resistor does not arrive at a pre-determined value, the testing machine increases the level of the write voltage. Furthermore, a resistive memory utilizing the testing machine is also provided.Type: GrantFiled: February 9, 2016Date of Patent: January 10, 2017Assignee: WINBOND ELECTRONICS CORP.Inventors: Lih-Wei Lin, Chia-Hung Lin, Tsung-Huan Tsai, Ju-Chieh Cheng, I-Hsien Tseng
-
Publication number: 20160276027Abstract: A resistive memory and a data writing method for a resistive memory cell thereof are provided. The method includes: receiving and decoding a column address signal for generating a decoded result, and providing a word line voltage to a word line of the resistive memory cell; providing a constant current to one of a bit line and a source line of the resistive memory cell, and coupling a reference ground voltage to another one of the bit line and the source line of the resistive memory cell.Type: ApplicationFiled: December 22, 2015Publication date: September 22, 2016Inventors: Lih-Wei Lin, I-Hsien Tseng, Ju-Chieh Cheng, Chia-Hung Lin, Tsung-Huan Tsai, Po-Wei Huang
-
Publication number: 20160240268Abstract: A measurement system including a testing machine and a resistive memory is provided. The resistive memory includes a first storage cell. The first storage cell includes a transistor and a variable resistor. During a specific period, the testing machine provides a write voltage to change the state of the variable resistor. During a maintaining period, the testing machine maintains the level of the write voltage and measures the current passing through the variable resistor. When the current passing through the variable resistor does not arrive at a pre-determined value, the testing machine increases the level of the write voltage. Furthermore, a resistive memory utilizing the testing machine is also provided.Type: ApplicationFiled: February 9, 2016Publication date: August 18, 2016Inventors: LIH-WEI LIN, CHIA-HUNG LIN, TSUNG-HUAN TSAI, JU-CHIEH CHENG, I-HSIEN TSENG