Patents by Inventor Ju-Chien Chiang

Ju-Chien Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7179701
    Abstract: A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: February 20, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ju-Wang Hsu, Jyu-Horng Shieh, Ju-Chien Chiang
  • Patent number: 7179715
    Abstract: The formation of gate spacers on the sides of a gate structure on a semiconductor substrate is provided. In one embodiment, a gate structure is formed on a gate insulator layer of the semiconductor substrate. A liner layer is formed over the exposed surfaces of the substrate, the gate insulator layer, and the gate structure. A layer of gate spacer material is formed over the liner layer. Thereafter, gate spacers are formed from the layer of gate spacer material. A protection layer is formed over portions of the liner layer, gate structure, and the gate spacers. The protection layer is etched back. A first wet etch procedure is performed to remove exposed portions of the liner layer. The protection layer is removed and a second wet etch procedure is performed to remove substantially a top portion and a bottom portion of the liner layer.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: February 20, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Chien Chiang, Shu-Huei Sun, Li-Te S. Lin
  • Publication number: 20060216918
    Abstract: The formation of gate spacers on the sides of a gate structure on a semiconductor substrate is provided. In one embodiment, a gate structure is formed on a gate insulator layer of the semiconductor substrate. A liner layer is formed over the exposed surfaces of the substrate, the gate insulator layer, and the gate structure. A layer of gate spacer material is formed over the liner layer. Thereafter, gate spacers are formed from the layer of gate spacer material. A protection layer is formed over portions of the liner layer, gate structure, and the gate spacers. The protection layer is etched back. A first wet etch procedure is performed to remove exposed portions of the liner layer. The protection layer is removed and a second wet etch procedure is performed to remove substantially a top portion and a bottom portion of the liner layer.
    Type: Application
    Filed: March 22, 2005
    Publication date: September 28, 2006
    Inventors: Ju-Chien Chiang, Shu-Huei Sun, Li-Te Lin
  • Publication number: 20060063322
    Abstract: A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.
    Type: Application
    Filed: September 21, 2004
    Publication date: March 23, 2006
    Inventors: Ju-Wang Hsu, Jyu-Horng Shieh, Ju-Chien Chiang
  • Publication number: 20050092348
    Abstract: The present invention provides aqueous compositions for cleaning integrated circuit substrates. Specifically, in the cleaning of an integrated circuit substrate, disclosed is a method for removing the by-products of the high-k dielectric dry etch process from the integrated circuit substrate, the method including: contacting the integrated circuit substrate with an aqueous composition including an amount, effective for the purpose of a (a) hydrogen fluoride, followed by (b) a mixture of hydrogen peroxide with a compound selected from the group consisting of ammonium hydroxide, hydrochloric acid and sulfuric acid.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 5, 2005
    Inventors: Ju-Chien Chiang, Ming-Huan Tsai, Huan-Just Lin, Yuan-Hung Chiu, Hun-Jan Tao