Abstract: A semiconductor memory device featuring redundant output switches for routing all data transactions to corresponding redundant columns instead of defective columns. The memory device includes an ordinary decoder and an ordinary memory cell array having a plurality of ordinary columns. The ordinary decoder is provided for decoding an address signal to drive one of the ordinary memory cells in the ordinary columns. The memory device also includes a redundant memory cell array, a redundant decoder and a redundant switch circuit. The redundant memory cell array has a plurality of redundant columns adapted to replace defective columns in the ordinary columns. The redundant decoder has a plurality of redundant decode circuits, in which a redundant decode circuit provides a redundant decode signal to the corresponding redundant column for driving it.

Abstract: A semiconductor memory device featuring redundant output switches for routing all data transactions to corresponding redundant columns instead of defective columns. The memory device includes an ordinary decoder and an ordinary memory cell array having a plurality of ordinary columns. The ordinary decoder is provided for decoding an address signal to drive one of the ordinary memory cells in the ordinary columns. The memory device also includes a redundant memory cell array, a redundant decoder and a redundant switch circuit The redundant memory cell array has a plurality of redundant columns adapted to replace defective columns in the ordinary columns. The redundant decoder has a plurality of redundant decode circuits, in which a redundant decode circuit provides a redundant decode signal to the corresponding redundant column for driving it.