Abstract: A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.

Abstract: A three-dimensional semiconductor device includes a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.

Abstract: A three-dimensional semiconductor device includes a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.

Abstract: A semiconductor device includes a substrate, gate electrodes and interlayer insulating layers alternately stacked on the substrate, channel regions penetrating through the gate electrodes and the interlayer insulating layers, a conductive layer penetrating through the gate electrodes and the interlayer insulating layers, an insulating layer covering an upper surface of the conductive layer, a contact plug penetrating through the insulating layer and connected to the conductive layer, and an air gap formed in the conductive layer. The conductive layer is connected to the substrate and extends between two groups of the channel regions. The air gap is defined by the contact plug, insulating layer and an inner sidewall of the conductive layer.

Abstract: A semiconductor apparatus includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, channel regions penetrating through the gate electrodes and the interlayer insulating layers, a conductive layer extending from an uppermost layer among the interlayer insulating layers to the substrate by penetrating through the gate electrodes and the interlayer insulating layers between the channel regions, and having an uneven pattern on an outer side wall thereof, a spacer layer disposed on the outer side wall, and a barrier layer disposed on at least one side surface of the spacer layer, wherein the spacer layer and the barrier layer have different etch selectivities.

Abstract: A semiconductor apparatus includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, channel regions penetrating through the gate electrodes and the interlayer insulating layers, a conductive layer extending from an uppermost layer among the interlayer insulating layers to the substrate by penetrating through the gate electrodes and the interlayer insulating layers between the channel regions, and having an uneven pattern on an outer side wall thereof, a spacer layer disposed on the outer side wall, and a barrier layer disposed on at least one side surface of the spacer layer, wherein the spacer layer and the barrier layer have different etch selectivities.

Abstract: A semiconductor device includes a substrate, gate electrodes and interlayer insulating layers alternately stacked on the substrate, channel regions penetrating through the gate electrodes and the interlayer insulating layers, a conductive layer penetrating through the gate electrodes and the interlayer insulating layers, an insulating layer covering an upper surface of the conductive layer, a contact plug penetrating through the insulating layer and connected to the conductive layer, and an air gap formed in the conductive layer. The conductive layer is connected to the substrate and extends between two groups of the channel regions. The air gap is defined by the contact plug, insulating layer and an inner sidewall of the conductive layer.

Abstract: A semiconductor device including a plug; a lower insulating film surrounding a lower sidewall of the plug; a spacer surrounding an upper sidewall of the plug; and a first interconnection line on the plug, the lower insulating film, and the spacer, the first interconnection line being in contact with an upper surface of the plug, wherein an upper portion of the spacer protrudes higher than the upper surface of the plug.