Abstract: A negatively delayed signal generating circuit for compensating a duty rate of an input signal, wherein the negatively delayed signal has a larger frequency than that of the input signal and a stable duty rate regardless of the duty rate of the input signal, thereby being stably applicable to a memory device requiring a high speed operation.

Abstract: An internal constant voltage control circuit for a semiconductor memory device includes a current source for generating voltage in accordance with current when power is turned on, a bias circuit for outputting a first bias voltage when power is turned on, a first level shifter for receiving the output voltage of the current source and outputting a first voltage, a second level shifter for receiving the output voltage of the bias circuit and outputting a second voltage, and a buffer for differentially amplifying the output voltage of the first level shifter and the output voltage of the second level shifter, and generating an internal voltage. The circuit decreases operation current by reducing an internal voltage during a low temperature operation and securing a timing margin between signals, thereby stabilizing a low temperature operation.