Patents by Inventor Ju-Hsuan Ko

Ju-Hsuan Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuits and methods therefor
    Patent number: 10177021
    Abstract: Aspects of the present disclosure are directed to methods and apparatuses involving a chip carrier having openings therein that align integrated circuit (IC) chips relative to an alignment feature. The IC chips and carrier are tested, such as by final testing the affixed IC chips after manufacture, and further testing after subjecting the affixed IC chips to one or more stress conditions. A test probe is aligned to one or more contacts on each chip based on the location of an alignment feature of the carrier relative to the opening in which the IC chip being tested is located. Responsiveness of the IC chip, before and after application of the one or more stress conditions, can be assessed by probing the IC chip via the aligned test probe, and assessing electrical signals received over the test probe.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 8, 2019
    Assignee: NXP B.V.
    Inventors: Chung Hsiung Ho, Wen-Hsuan Lin, Ju-Hsuan Ko, Chih Hung Chang
  • INTEGRATED CIRCUITS AND METHODS THEREFOR
    Publication number: 20170200657
    Abstract: Aspects of the present disclosure are directed to methods and apparatuses involving a chip carrier having openings therein that align integrated circuit (IC) chips relative to an alignment feature. The IC chips and carrier are tested, such as by final testing the affixed IC chips after manufacture, and further testing after subjecting the affixed IC chips to one or more stress conditions. A test probe is aligned to one or more contacts on each chip based on the location of an alignment feature of the carrier relative to the opening in which the IC chip being tested is located. Responsiveness of the IC chip, before and after application of the one or more stress conditions, can be assessed by probing the IC chip via the aligned test probe, and assessing electrical signals received over the test probe.
    Type: Application
    Filed: January 13, 2016
    Publication date: July 13, 2017
    Inventors: Chung Hsiung Ho, Wen-Hsuan Lin, Ju-Hsuan Ko, Chih Hung Chang