Patents by Inventor Ju-Ik Lee

Ju-Ik Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190189448
    Abstract: Disclosed herein is an apparatus for processing a substrate that forms a hole in a substrate while reducing a burr in the hole so that a module device can be inserted into the hole to reduce the thickness of a display device, and the display device using the apparatus. The apparatus for processing the substrate comprises a body configured to operably be rotatable, and a cylindrical cutting tip at an end of the body. The bottom surface of the cutting tip is in an acute angle with respect to a contact surface of the substrate to allow formation of a groove at the substrate.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Inventors: Jeong Kweon PARK, Jeong Joon Lee, Ju Ik Hong, Sang Chul Lee, Jangcheol Kim, Ik Hyun Kuon, Tagyoung CHOI, Jinwook Kwak
  • Patent number: 9824726
    Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: November 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hoon Han, Dong-Wan Kim, Ju-Ik Lee
  • Publication number: 20170025416
    Abstract: A capacitor structure includes a plurality of lower electrodes, a support pattern structure, a dielectric layer, and an upper electrode. The lower electrodes are formed on a substrate. The support pattern structure is formed between the lower electrodes, and includes a lower support pattern and an upper support pattern structure over the lower support pattern. The upper support pattern structure includes a plurality of upper support patterns spaced apart from each other in a direction substantially perpendicular to a top surface of the substrate. The dielectric layer is formed on the lower electrodes and the support pattern structure. The upper electrode is formed on the dielectric layer. A sum of thicknesses of the plurality of upper support patterns in the direction substantially perpendicular to the top surface of the substrate is about 35% to about 85% of a total thickness of the upper support pattern structure.
    Type: Application
    Filed: March 11, 2016
    Publication date: January 26, 2017
    Inventors: Jung-Hoon Han, Jong-Min Lee, Dong-Wan Kim, Ju-Ik Lee
  • Publication number: 20160267949
    Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.
    Type: Application
    Filed: May 25, 2016
    Publication date: September 15, 2016
    Inventors: JUNG-HOON HAN, DONG-WAN KIM, JU-IK LEE
  • Patent number: 9379002
    Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hoon Han, Dong-Wan Kim, Ju-Ik Lee