Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract: A stacked semiconductor package may include: a substrate; semiconductor packages stacked on the substrate; an interconnection member formed on edges of the semiconductor packages; and a conductive reinforcement member formed on the interconnection member. Each of the semiconductor packages may include a conductive line. The interconnection member may electrically connect the conductive line of the semiconductor packages to the conductive line of at least one other semiconductor package.

Abstract: A semiconductor device and methods of forming the same are provided. The methods may include forming a hole in a preliminary semiconductor substrate, forming an insulating layer in the hole of the preliminary semiconductor substrate, forming a plating conductive layer on the insulating layer and the preliminary semiconductor substrate, forming a seed metal layer contacting the plating conductive layer at a lower portion of the hole and growing the seed metal layer to form a through-silicon via (TSV). The TSV may be formed through an electroplating process such that the seed metal layer grows from the lower portion of the hole to an upper portion of the hole.

Abstract: Provided is a semiconductor plating system for plating a semiconductor object with a desired layer. The semiconductor plating system include a plating tank configured to accommodate a plating solution for use in plating the semiconductor object, and a plating solution induction device configured to induce the plating solution to spirally flow toward the semiconductor object.

Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

Abstract: A method of forming a wire structure connecting to a bonding pad of a semiconductor chip includes depositing a passivation layer on an active surface of the semiconductor chip, depositing a seed metal layer on the bonding pad and the passivation layer, depositing a metal layer on the seed metal layer, etching selected portions of the seed metal layer, leaving unetched a first area, overlapping the bonding pad and a second area overlapping a connection pad, wherein the wire structure is formed by the metal layer being electrically connected to the bonding pad and the connection pad, but floating from the passivation layer, and depositing an insulting layer on the wire structure.

Abstract: A wiring structure may include a pad, a conductive pattern and an insulating photoresist structure. The pad may be provided on a body and electrically connected to a circuit unit of the body. The conductive pattern may be provided on the body and may be electrically connected to the pad. The insulating photoresist structure may be provided on a surface of the conductive pattern. The insulating photoresist structure may have a contact hole through which the conductive pattern may be partially exposed. The insulating photoresist structure may be fabricated by providing a photosensitive photoresist film on the conductive layer, and patterning the photosensitive photoresist film by two photo processes.