Abstract: A signal detector circuit arrangement for detecting synchronizing pulses contained in a digital television signal by the use of a separating stage wherein, during the time intervals in which television signal portions are separated in the separating stage and at the same time an instantaneous sampling value exceeds a stored sampling value in the direction of the level of the synchronizing pulses, the stored sampling value is replaced by the instantaneous sampling value and simultaneously a marker pulse is generated. In each time interval between consecutive synchronizing pulses, the stored sampling value is erased at a presettable instant which is identical for all the time intervals. The final marker pulse of such an erasing procedure marks a detected synchronizing pulse.