Abstract: A frequency-jitter-controller for a power-converter is provided, and which includes a first and a second capacitance units, a first and a second charge-discharge control units, a comparing unit and a control unit. Both capacitance units are charged to a crossing-voltage during a charging phase and discharged to a reference voltage and a clamp voltage respectively during a discharging-phase in response to operations of both charge-discharge control units. The comparing unit outputs a pulse signal, compares voltages of both capacitance units during the charging phase, and compares the voltage of the first capacitance unit and the reference voltage during the discharging phase. The control unit generates a frequency jitter control signal according to the pulse signal to adjust a rising rate of the voltage on the second capacitance unit, so as to change a frequency of the pulse signal, and thus reduce EMI generated by switching switch-elements in the power-converter.

Abstract: A power conversion apparatus and an over current protection (OCP) method thereof are provided. The OCP method includes generating a pulse-width-modulation (PWM) signal according to a loading status of an electronic device, so as to switch a power switch in the power conversion apparatus and thus making the power conversion apparatus providing an output voltage to the electronic device; generating an OCP reference signal with variable slope according to a feedback signal related to the loading status of the electronic device and a system operation voltage of a PWM controller chip in the power conversion apparatus that is used for generating the PWM signal; and comparing a sensing voltage corresponding to a current following through the power switch on a resistor, and the OCP reference signal with variable slope to determine whether to activate an OCP mechanism to control the PWM controller chip whether to generate the PWM signal.

Abstract: A heterodyne dual-slope frequency generation method for the load change of the power supply, which comprises a power transformer, a feedback control circuit, and a dual-slope charge-discharge circuit. The power supply generates different charge current to fit different operating mode through the feedback control circuit, feedback voltage generated into power transformer, and passes through the dual-slope charge-discharge circuit in accordance with the different outer load device and the different outer voltage rising speed. When the outer loading is changed, the feedback control circuit detects error voltage, feeds through power transformer, further changes the supplied current, and finally automatically adjusts the driving current and the output power.

Abstract: A power conversion apparatus and a brown-out protection method are provided. The brown-out protection method includes sampling a rectification signal relating to an AC voltage received by the power conversion apparatus by adopting a discrete sampling means; and when a peak value of the sampled rectification signal has reached to a predetei mined value within a predetermined duration, making a pulse width modulation (PWM) control chip in the power conversion apparatus provide a PWM signal to switch a power switch in the power conversion apparatus, and thereby making the power conversion apparatus provide an output voltage to an electronic device; otherwise, making the PWM control chip to stop providing the PWM signal.

Abstract: A power conversion apparatus and an over current protection (OCP) method thereof are provided. The OCP method includes generating a pulse-width-modulation (PWM) signal according to a loading status of an electronic device, so as to switch a power switch in the power conversion apparatus and thus making the power conversion apparatus providing an output voltage to the electronic device; generating an OCP reference signal with variable slope according to a feedback signal related to the loading status of the electronic device and a system operation voltage of a PWM controller chip in the power conversion apparatus that is used for generating the PWM signal; and comparing a sensing voltage corresponding to a current following through the power switch on a resistor, and the OCP reference signal with variable slope to determine whether to activate an OCP mechanism to control the PWM controller chip whether to generate the PWM signal.

Abstract: A heterodyne dual-slope frequency generation method for the load change of the power supply, which comprises a power transformer, a feedback control circuit, and a dual-slope charge-discharge circuit. The power supply generates different charge current to fit different operating mode through the feedback control circuit, feedback voltage generated into power transformer, and passes through the dual-slope charge-discharge circuit in accordance with the different outer load device and the different outer voltage rising speed. When the outer loading is changed, the feedback control circuit detects error voltage, feeds through power transformer, further changes the supplied current, and finally automatically adjusts the driving current and the output power.

Abstract: A frequency-jitter-controller for a power-converter is provided, and which includes a first and a second capacitance units, a first and a second charge-discharge control units, a comparing unit and a control unit. Both capacitance units are charged to a crossing-voltage during a charging phase and discharged to a reference voltage and a clamp voltage respectively during a discharging-phase in response to operations of both charge-discharge control units. The comparing unit outputs a pulse signal, compares voltages of both capacitance units during the charging phase, and compares the voltage of the first capacitance unit and the reference voltage during the discharging phase. The control unit generates a frequency jitter control signal according to the pulse signal to adjust a rising rate of the voltage on the second capacitance unit, so as to change a frequency of the pulse signal, and thus reduce EMI generated by switching switch-elements in the power-converter.

Abstract: A power conversion apparatus with adjustable leading-edge-blanking (LEB) time and an over current protection (OCP) method thereof are provided. In the OCP method, a pulse-width-modulation (PWM) signal is generated according to the loading status of an electronic device to switch a power switch in the power conversion apparatus and thus the power conversion apparatus to supply an output voltage to the electronic device. A variable or fixed LEB signal is generated according to the PWM signal and the rising and falling edges of a spike signal induced at turn-on instant of the power switch. The PWM signal is constantly/continuously generated to switch the power switch during an enabling period/phase of the variable or fixed LEB signal, and whether an over current is produced in the power conversion apparatus is constantly detected to determine whether to activate an OCP mechanism during a disabling period/phase of the variable or fixed LEB signal.

Abstract: Power management integrated circuit and related devices. A clock generator generates a periodic signal. Based on the periodic signal and a feedback signal, a pulse width modulator generates a control signal, based on which a driver drives a power switch. A power terminal is connected to an external capacitor. A linear regulator connected to the power terminal generates and supplies an internal power source. Powered by the internal power source, a bandgap generator provides a bandgap reference voltage. A standby control terminal receives a standby signal. When the standby signal is asserted, the clock generator, the pulse with modulator and the driver are at a disabled state, and the linear regulator and the bandgap generator at an enabled state.

Abstract: A phase recovery circuit for avoiding noise interfering with the clock signal generated from an oscillator is disclosed. The phase recovery circuit includes a noise detector, a phase detector, and a phase locker. The noise detector detects noise and accordingly generates a noise detecting signal. The phase detector is triggered by the noise detecting signal for detecting the phase of the clock signal and accordingly generating a phase detecting signal. The phase locker locks the phase of the clock signal to a predetermined phase within a predetermined period after the occurrence of the noise detecting signal, and after the predetermined period, the phase locker releases the clock signal. In this way, the phase of the clock signal is not affected by noise.

Abstract: A phase recovery circuit for avoiding noise interfering with the clock signal generated from an oscillator is disclosed. The phase recovery circuit includes a noise detector, a phase detector, and a phase locker. The noise detector detects noise and accordingly generates a noise detecting signal. The phase detector is triggered by the noise detecting signal for detecting the phase of the clock signal and accordingly generating a phase detecting signal. The phase locker locks the phase of the clock signal to a predetermined phase within a predetermined period after the occurrence of the noise detecting signal, and after the predetermined period, the phase locker releases the clock signal. In this way, the phase of the clock signal is not affected by noise.

Abstract: A digital frequency jittering circuit for varying a switching frequency of a power supply is disclosed. The digital frequency jittering circuit includes a random data generator, an analog to digital functional module, and a digital to analog functional module. The random data generator has an oscillator for generating an oscillating signal having the switching frequency; a delay module for delaying the oscillating signal by first and second delay amounts to generate first and second delayed signals, wherein the first delay amount is not equal to the second delay amount; and a phase error detecting module for detecting an phase error between the first and the second delayed signals to generate a random data. The analog to digital functional module converts the random data into a digital random value. The digital to analog functional module varies the switching frequency of the oscillating signal according to the digital random value.

Abstract: A digital frequency jittering circuit for varying a switching frequency of a power supply is disclosed. The digital frequency jittering circuit includes a random data generator, an analog to digital functional module, and a digital to analog functional module. The random data generator has an oscillator for generating an oscillating signal having the switching frequency; a delay module for delaying the oscillating signal by first and second delay amounts to generate first and second delayed signals, wherein the first delay amount is not equal to the second delay amount; and a phase error detecting module for detecting an phase error between the first and the second delayed signals to generate a random data. The analog to digital functional module converts the random data into a digital random value. The digital to analog functional module varies the switching frequency of the oscillating signal according to the digital random value.

Abstract: A dual loop voltage regulation circuit of power supply chip is provided, comprising a capacitor for providing a voltage signal, a comparator for comparing a first reference voltage signal and the voltage signal to output forward or backward trigger signal, a first switch triggered by a forward trigger signal, a second switch triggered by a backward trigger signal, a first operational amplifier generating a first drive signal while the first and second switches are on, a first transistor switch triggered to be on by a first drive signal to provide a current source loop, a third switch triggered by a forward trigger signal, a fourth switch triggered by a backward trigger signal, a second operational amplifier generating a second drive signal while the third and fourth switches are on, and a second transistor switch triggered to be on by a second drive signal to provide a current sink loop.

Abstract: A dual loop voltage regulation circuit of power supply chip is provided, comprising a capacitor for providing a voltage signal, a comparator for comparing a first reference voltage signal and the voltage signal to output forward or backward trigger signal, a first switch triggered by a forward trigger signal, a second switch triggered by a backward trigger signal, a first operational amplifier generating a first drive signal while the first and second switches are on, a first transistor switch triggered to be on by a first drive signal to provide a current source loop, a third switch triggered by a forward trigger signal, a fourth switch triggered by a backward trigger signal, a second operational amplifier generating a second drive signal while the third and fourth switches are on, and a second transistor switch triggered to be on by a second drive signal to provide a current sink loop.

Abstract: A protection circuit of the memory module and the method thereof is provided. The protection circuit comprises: a first voltage comparing unit, which compares a reference voltage signal with a voltage level signal to output a first driving signal; a transistor switch, which is connected among the output terminal of the first voltage comparing unit and the input terminal of the second voltage comparing unit and a power end, wherein the voltage level signal and the threshold voltage signal is compared by the second voltage comparing unit so as to output a second driving signal to a logical algorithm unit, and a logical algorithm is conducted between the second driving signal and system enable signal to output a third driving signal; and a soft start enable unit for receiving the third driving signal so as to enable a soft start process.

Abstract: A protection circuit of the memory module and method thereof are provided. The protection circuit includes: a first voltage comparing unit, which compares a reference voltage signal with a voltage level signal to output a first driving signal; a transistor switch, which is connected among the output terminal of the first voltage comparing unit and the input terminal of the second voltage comparing unit and a power end, wherein the voltage level signal and the threshold voltage signal is compared by the second voltage comparing unit so as to output a second driving signal to a logical algorithm unit, and a logical algorithm is conducted between the second driving signal and system enable signal to output a third driving signal; and a soft start enable unit for receiving the third driving signal so as to enable a soft start process.