Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

Abstract: An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier is coupled to the input amplifier and outputting an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced. The diode device includes a variable resistor to increase the barrier voltage of the diode device.

Abstract: A display apparatus and a driving method of the same are provided. The display apparatus includes a display panel, a gate driver circuit, and a source driver circuit. During a functional sub-period of a frame period, the gate driver circuit simultaneously drives a plurality of gate lines, and the source driver circuit drives a plurality of source lines, so as to perform a function on a plurality of pixels connected to the gate lines. In a scan sub-period of the frame period, the gate driver circuit drives the gate lines according to a scan sequence, and the source driver circuit correspondingly drives the source lines according to the scan sequence of the gate driver circuit in the first scan sub-period, so as to display an image.

Abstract: In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.

Abstract: A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.

Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.

Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

Abstract: A power rail clamp circuit is coupled between a system power supply and a ground for alleviating an electrostatic discharge effect. The power rail clamp circuit includes a first conduction circuit, a second conduction circuit, an AND gate module and a switch module. The AND gate module receives a first conduction signal generated by the first conduction circuit and a second conduction signal generated by the second conduction circuit to generate an enabling signal. The switch module conducts the power rail clamp circuit according to the enabling signal, to process an electrostatic discharge operation. The first conduction circuit is operated to prevent a high voltage value of the system power supply, and the second conduction circuit is operated to prevent a short initiation period of the system power supply.

Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.

Abstract: An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier is coupled to the input amplifier and outputting an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced. The diode device includes a variable resistor to increase the barrier voltage of the diode device.

Abstract: A display apparatus and a gate driving method thereof are provided. The display apparatus includes a display panel and a gate driver. The display panel has a plurality of gate lines. Output terminals of the gate driver are coupled to the gate lines in a one-to-one manner. The gate driver is configured to drive the gate lines according to a scrambled scan sequence.

Abstract: An amplifier circuit with an overshoot suppress scheme is provided. The amplifier circuit includes an input amplifier, an output amplifier and a diode device. The output amplifier is coupled to the input amplifier and outputs an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.

Abstract: An output circuit with electrostatic discharge (ESD) protection in a semiconductor chip includes a first metal oxide semiconductor (MOS) transistor and a first resistor. The first MOS transistor includes a first terminal coupled to an output pad of the semiconductor chip, a bulk terminal and a gate terminal. The first resistor is coupled between the bulk terminal of the first MOS transistor and a first power supply terminal.

Abstract: A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.

Abstract: A gate driver, a display apparatus having the same, and a gate driving method are provided. The display apparatus includes a plurality of pixels, a data driver circuit, and a gate driver circuit. The gate driver circuit includes M groups of gate channels. Each of the M groups of gate channels includes a control circuit and an output buffer. The control circuit receives a power supply voltage from a power supply circuit and generates a modulated supply voltage. The output buffer is connected to the control circuit, the output buffer is powered by the modulated supply voltage to output a gate signal to a gate line of the display panel, wherein a driving pulse of the gate signal is shaped during a charge period according to the modulated supply voltage, and the shape of the driving pulse of the gate signal is maintained during a pre-charge period.

Abstract: A display panel, a manufacturing method thereof, and a driving method thereof are provided. The display panel includes at least one source line and a plurality of pixel circuits. The source terminal of each of the pixel circuits is coupled to the source line. The pixel circuits include a near pixel circuit and a far pixel circuit. The distance from the near pixel circuit to a source driver is less than the distance from the far pixel circuit to the source driver. The input impedance (in turn-on state) of the source terminal of the near pixel circuit is greater than the input impedance (in turn-on state) of the source terminal of the far pixel circuit, so as to compensate the source line impedance difference at different locations of the same source line.

Abstract: A source driver apparatus and an operating method thereof are provided. The source driver apparatus can drive a plurality of source lines of a display panel, wherein the display panel further comprising a gate driver apparatus. The source driver apparatus includes driving channels and a delay control circuit. The driving channels output source driving signals. The delay control circuit controls the driving channels to change delay times of the source driving signals within the same period, such that the delay times of the source driving signals respectively correspond to distances from the source lines to the gate driver apparatus.

Abstract: In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.

Abstract: A panel driver integrated circuit (IC) and a cooling method of the panel driver IC are provided. The panel driver IC includes a data encoder, a level shifter, a Digital-to-Analog Converter (DAC), a rearrangement circuit and an output buffer. The data encoder receives and selectively changes an original data for outputting to the level shifter. An input terminal and an output terminal of the level shifter are coupled to an output terminal of the data encoder and a data input terminal of the DAC, respectively. The output terminals of the rearrangement circuit are respectively coupled to the reference voltage input terminals of the DAC for providing different reference voltages. The rearrangement circuit correspondingly rearranges the order of the reference voltages according to the operation of the data encoder. An input terminal of the output buffer is coupled to an output terminal of the DAC.