Abstract: A module for generating real-time, multiple-resolution video streams and the architecture thereof are disclosed. A module for generating multiple-resolution video streams as well as the architecture thereof for use with a video encoder includes a system bus, an external memory and a main processor. The main processor and the external memory are coupled to the system bus. The main processor includes a microprocessor, a main arithmetic unit and a secondary arithmetic unit. By applying the present invention, a less time-consuming arithmetic module can synchronously perform together with a more time-consuming arithmetic module, thereby reducing idle time and increasing hardware efficiency and parallelism.

Abstract: A module for generating real-time, multiple-resolution video streams and the architecture thereof are disclosed. A module for generating multiple-resolution video streams as well as the architecture thereof for use with a video encoder includes a system bus, an external memory and a main processor. The main processor and the external memory are coupled to the system bus. The main processor includes a microprocessor, a main arithmetic unit and a secondary arithmetic unit. By applying the present invention, a less time-consuming arithmetic module can synchronously perform together with a more time-consuming arithmetic module, thereby reducing idle time and increasing hardware efficiency and parallelism.

Abstract: Provided is an external memory accessing architecture for use with IC comprising a first bus connected to an external memory and having n-bit data width; a first buffer unit of k serially connected first buffers each having n-bit data width, a first one of the first buffers connected to the external memory via the first bus; a second buffer unit comprising a second buffer having k*n-bit data width, the second buffer connected to the first buffers; a second bus connected to the second buffer for transferring k*n-bit data; an output unit connected to the second buffer unit and comprising a multiplexer; and a controller connected to the output unit, the second bus, and the external memory respectively such that the controller is able to read data from the external memory or transfer data thereto via the second bus and at least one control signal in higher transfer rate.