Patents by Inventor Jumi Yun
Jumi Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230380164Abstract: A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.Type: ApplicationFiled: March 2, 2023Publication date: November 23, 2023Inventors: Kyeonghoon Park, Inhwan Baek, Jaebok Baek, Jeehoon Han, Seungyoon Kim, Heesuk Kim, Byoungjae Park, Jongseon Ahn, Jumi Yun
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Publication number: 20220238555Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Bio KIM, Yujin KIM, Philouk NAM, Youngseon SON, Kyongwon AN, Jumi YUN, Woojin JANG
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Patent number: 11329063Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.Type: GrantFiled: April 14, 2020Date of Patent: May 10, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Bio Kim, Yujin Kim, Philouk Nam, Youngseon Son, Kyongwon An, Jumi Yun, Woojin Jang
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Publication number: 20210036012Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.Type: ApplicationFiled: April 14, 2020Publication date: February 4, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Bio KIM, Yujin KIM, Philouk NAM, Youngseon SON, Kyongwon AN, Jumi YUN, Woojin JANG
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Patent number: 9490371Abstract: A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.Type: GrantFiled: November 12, 2014Date of Patent: November 8, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Jin Noh, Bio Kim, Kwangmin Park, Jaeyoung Ahn, SeungHyun Lim, JaeHo Choi, Jumi Yun, Ji-Hoon Choi
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Patent number: 9437607Abstract: A semiconductor device has a vertical channel and includes a first tunnel insulating layer adjacent to a blocking insulating layer, a third tunnel insulating layer adjacent to a channel pillar, and a second tunnel insulating layer between the first and third tunnel insulating layers. The energy band gap of the third tunnel insulating layer is smaller than that of the first tunnel insulating layer and is larger than that of the second tunnel insulating layer.Type: GrantFiled: August 15, 2013Date of Patent: September 6, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kwangmin Park, Byongju Kim, Jumi Yun, Jaeyoung Ahn
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Patent number: 9397114Abstract: Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.Type: GrantFiled: May 18, 2012Date of Patent: July 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jumi Yun, Kwangmin Park, Dongchul Yoo, Byong-hyun Jang
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Publication number: 20150194440Abstract: A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.Type: ApplicationFiled: November 12, 2014Publication date: July 9, 2015Inventors: Young-Jin Noh, Bio Kim, Kwangmin Park, Jaeyoung Ahn, SeungHyun Lim, JaeHo Choi, Jumi Yun, Ji-Hoon Choi
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Publication number: 20140073099Abstract: A semiconductor device has a vertical channel and includes a first tunnel insulating layer adjacent to a blocking insulating layer, a third tunnel insulating layer adjacent to a channel pillar, and a second tunnel insulating layer between the first and third tunnel insulating layers. The energy band gap of the third tunnel insulating layer is smaller than that of the first tunnel insulating layer and is larger than that of the second tunnel insulating layer.Type: ApplicationFiled: August 15, 2013Publication date: March 13, 2014Inventors: KWANGMIN PARK, BYONGJU KIM, JUMI YUN, JAEYOUNG AHN
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Publication number: 20120295409Abstract: Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.Type: ApplicationFiled: May 18, 2012Publication date: November 22, 2012Inventors: Jumi Yun, Kwangmin Park, Dongchul Yoo, Byong-hyun Jang
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Publication number: 20120208347Abstract: Methods of fabricating a three-dimensional semiconductor device are provided. Methods may include forming a stack structure including first layers and second layers alternately stacked on a substrate, patterning the stack structure to form at least one isolation trench, forming channel structures penetrating the stack structure and being spaced apart from the isolation trench, and forming upper interconnection lines on the stack structure to connect the channel structures to each other. An isolation trench may be formed prior to formation of the channel structures.Type: ApplicationFiled: February 7, 2012Publication date: August 16, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Hwang, Kwangmin Park, Woonkyung Lee, Jintaek Park, Byong-byun Jang, Jumi Yun