Patents by Inventor Ju-peng Chen

Ju-peng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8161354
    Abstract: A flash memory controller includes a control unit, a buffer, an error correction code (ECC) module, and a configuring unit. The flash memory has a data area for storing the data content and a first spare area for storing a first ECC value corresponding to the data content. The ECC module utilizes the data content for generating a second ECC value and comparing the second ECC value with the first ECC value to determine whether the data content comprises a plurality of errors. The configuring unit computes the amount of the errors to determine whether the amount of the errors exceeds a predetermined threshold. If The configuring unit configures the data area and assigns a portion of the data area to be a second spare area. The first and the second spare area are associated with the ECC capability to allow the ECC module to correct the errors.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: April 17, 2012
    Assignee: Genesys Logic, Inc.
    Inventor: Ju-peng Chen
  • Patent number: 8069396
    Abstract: A storage device for refreshing pages of a flash memory comprises a flash memory, an ECC detector and a controller. The flash memory has a plurality of pages, and each page comprises a data area for storing data and a spare area for storing error correction code (ECC) corresponding to the data. The ECC detector is used to get the number of error bits of each page. The controller coupled to the ECC detector is used for storing data and ECC in a first page to a second page when a number of used bytes of the ECC stored in a spare area of the first page exceeds a first predetermined value. A number of used bytes of the ECC stored in a spare area of the second page is less than the first predetermined value. The second page is a blank page.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: November 29, 2011
    Assignee: Genesys Logic, Inc.
    Inventors: Ju-peng Chen, Chih-jung Lin
  • Patent number: 7934053
    Abstract: A flash memory storage device for boosting efficiency in accessing flash memory is disclosed. The flash memory storage device provides a Multi-level cell (MLC) flash memory for storing data, a single-level cell (SLC) flash memory for storing data, and a control unit for determining whether to store a file into the MLC NAND flash memory or a SLC NAND flash memory based on the file's data characteristics.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: April 26, 2011
    Assignee: Genesys Logic, Inc.
    Inventors: Ju-peng Chen, Nei-chiung Perng
  • Patent number: 7778101
    Abstract: A memory module and a method of performing the same for access of an external electronic device are provided herein. The memory module includes a NAND-type flash memory, a dynamic random access memory (DRAM) unit, and a memory controller. The dynamic random access memory unit which is electrically connected to the NAND-type flash memory includes a dynamic random access memory and an internal power. The memory controller is used for controlling at least one of both the NAND-type flash memory and the dynamic random access memory unit. When the memory module is disconnected with the external electronic device, the internal power of the dynamic random access memory unit powers the dynamic random access memory, actively. Accordingly, data stored in the dynamic random access memory will be retained.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: August 17, 2010
    Assignee: Genesys Logic, Inc.
    Inventor: Ju-peng Chen
  • Publication number: 20100123661
    Abstract: A slide presentation system and a method of performing the same which are capable of providing a real-time interaction among conference presenter and attendees are disclosed. When a projector projects at least one slide to as map a screened image generated from a host, an image identifying unit identifies a pointer after an image capturing unit imaging the content expressed on the projected slide. After the pointer is identified, an orienting unit detects a two-dimension coordinate value with reference to where the pointer is pointed on the projected slide as the same as the screened image of the host. Then, the two-dimension coordinate values are transmitted to the host for determining an action of the pointer according to the two-dimension coordinate value with reference to the screened image of the host. By the present invention, the pointer pointing on the projected slide can be directly implemented as functioning a mouse.
    Type: Application
    Filed: November 19, 2008
    Publication date: May 20, 2010
    Applicant: GENESYS LOGIC, INC.
    Inventor: Ju-peng Chen
  • Publication number: 20100100797
    Abstract: A dual mode error correction code (ECC) apparatus for the flash memory and method thereof are described. The dual mode error correction code (ECC) apparatus includes a syndrome detection unit, a first ECC unit, a second ECC unit, a switch module, and an interface module. The syndrome detection unit detects the data content for computing the amount of errors in the data content to determine whether the amount of the errors exceeds a pre-determined threshold value. The first ECC unit corrects the errors in the data content based on a first coding mode. The second ECC unit corrects the errors in the data content based on a second coding mode. The switch module either switches to the first ECC unit for activating the first coding mode of the first ECC unit if the amount of the errors is fewer than a pre-determined threshold value or switches to the second ECC unit for activating the second coding mode of the second ECC unit if the amount of the errors is greater than the pre-determined threshold value.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 22, 2010
    Applicant: GENESYS LOGIC, INC.
    Inventor: Ju-peng Chen
  • Publication number: 20100100763
    Abstract: A flash memory controller having a configuring unit of error correction code (ECC) capability and method thereof are described. The flash memory controller includes a control unit, a buffer, an ECC module, and a configuring unit. The flash memory has a data area for storing the data content and a first spare area for storing a first ECC value corresponding to the data content. The ECC module utilizes the data content for generating a second ECC value and comparing the second ECC value with the first ECC value to determine whether the data content comprises a plurality of errors based on the compared result of the first ECC value and the second ECC value. The configuring unit computes the amount of the errors if the data content has the errors to determine whether the amount of the errors exceeds a predetermined threshold.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 22, 2010
    Applicant: GENESYS LOGIC, INC.
    Inventor: Ju-peng Chen
  • Publication number: 20100061133
    Abstract: A memory module and a method of performing the same for access of an external electronic device are provided herein. The memory module includes a NAND-type flash memory, a dynamic random access memory (DRAM) unit, and a memory controller. The dynamic random access memory unit which is electrically connected to the NAND-type flash memory includes a dynamic random access memory and an internal power. The memory controller is used for controlling at least one of both the NAND-type flash memory and the dynamic random access memory unit. When the memory module is disconnected with the external electronic device, the internal power of the dynamic random access memory unit powers the dynamic random access memory, actively. Accordingly, data stored in the dynamic random access memory will be retained.
    Type: Application
    Filed: September 5, 2008
    Publication date: March 11, 2010
    Applicant: GENESYS LOGIC, INC.
    Inventor: Ju-peng Chen
  • Publication number: 20100049904
    Abstract: A storage device includes a multi-level cell flash memory having a plurality of physical memory cells, a read controller, and a write controller. The physical memory cells form a first page and a second page. The write controller in response to a first request is used for writing first data into the first page, duplicating the first data as a second data and writing the second data into the second page. The read controller is used for adjusting the stored data value complying with a desired storing value. Each physical memory cell comprises four threshold voltage ranges indicative of two-bit logical values. The two-bit data is assigned as a first logical value accordingly in response to a two-bit data corresponding to a first and second threshold voltage ranges in a first physical memory cell. The two-bit data is assigned as a second logical value accordingly in response to a two-bit data corresponding to a third and fourth threshold voltage ranges in a second physical memory cell.
    Type: Application
    Filed: November 24, 2008
    Publication date: February 25, 2010
    Applicant: GENESYS LOGIC, INC.
    Inventor: Ju-peng Chen
  • Publication number: 20100037003
    Abstract: A flash memory control apparatus having a signal-converting module is described. The signal-converting module includes a primary controller, a signal-converting module, a data buffer, and a secondary controller. The primary controller generates a plurality of control signals based on a first control interface. The signal-converting module receiving a reading enable signal and a writing enable signal of the control signals and converts the reading enable signal and the writing enable signal into a writing/reading signal based on a second control interface. The data buffer stores the data from the primary controller according to the first control interface and stores the data from the flash memory according to the second control interface. The secondary controller transmits the writing/reading signal, a clock signal and a data strobe signal to the flash memory based on the second control interface.
    Type: Application
    Filed: December 3, 2008
    Publication date: February 11, 2010
    Applicant: GENESYS LOGIC, INC.
    Inventors: Ju-peng Chen, Yu-jen Hsu
  • Publication number: 20100037004
    Abstract: A storage system for backup data of a flash memory includes a flash memory for storing a first file, a detector for detecting a number of accesses to the first file, and a driving unit coupled to the detector. The driving unit is used for duplicating the first file as one or more second files when the number of accesses to the first file exceeds a predetermined value, and storing the one or more first files into the flash memory. If the access number is higher than the predetermined value, which indicates this file is more likely to be accessed, the invention automatically backups this file and accesses the backup file at the next access request for fear that the file is damaged by multiple access to the same file.
    Type: Application
    Filed: December 10, 2008
    Publication date: February 11, 2010
    Applicant: GENESYS LOGIC, INC.
    Inventor: Ju-peng Chen
  • Publication number: 20100011276
    Abstract: A storage device for refreshing pages of a flash memory comprises a flash memory, an ECC detector and a controller. The flash memory has a plurality of pages, and each page comprises a data area for storing data and a spare area for storing error correction code (ECC) corresponding to the data. The ECC detector is used to get the number of error bits of each page. The controller coupled to the ECC detector is used for storing data and ECC in a first page to a second page when a number of used bytes of the ECC stored in a spare area of the first page exceeds a first predetermined value. A number of used bytes of the ECC stored in a spare area of the second page is less than the first predetermined value. The second page is a blank page.
    Type: Application
    Filed: August 25, 2008
    Publication date: January 14, 2010
    Applicant: GENESYS LOGIC, INC.
    Inventors: Ju-peng Chen, Chih-jung Lin
  • Publication number: 20090204776
    Abstract: A system for securing an access to a flash memory is provided. The system includes a first flash memory storage device having a plurality of storage elements for storing data, and a host for accessing the first flash memory storage device. The host includes a control unit, a storing unit, and an identification unit. The control unit is used for generating an identification code and assigning the identification code into a random storage element selected from the plurality of storage elements, when the first flash memory storage device is to be accessed by the host at the first time. The storing unit is used for storing the identification code and a set address corresponding to the stored storage element.
    Type: Application
    Filed: April 3, 2008
    Publication date: August 13, 2009
    Applicant: GENESYS LOGIC, INC.
    Inventor: Ju-peng Chen
  • Publication number: 20090204746
    Abstract: A flash memory storage device for boosting efficiency in accessing flash memory is disclosed. The flash memory storage device provides a Multi-level cell (MLC) flash memory for storing data, a single-level cell (SLC) flash memory for storing data, and a control unit for determining whether to store a file into the MLC NAND flash memory or a SLC NAND flash memory based on the file's data characteristics.
    Type: Application
    Filed: April 16, 2008
    Publication date: August 13, 2009
    Applicant: GENESYS LOGIC, INC.
    Inventors: Ju-peng Chen, Nei-chiung Perng