Patents by Inventor Ju-Ri Kim
Ju-Ri Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7588983Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.Type: GrantFiled: February 4, 2008Date of Patent: September 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Weon-ho Park, Byoung-ho Kim, Hyun-khe Yoon, Seung-beom Yoon, Sung-chul Park, Ju-ri Kim, Kwang-Tae Kim, Jeong-wook Han
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Patent number: 7589376Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.Type: GrantFiled: August 27, 2008Date of Patent: September 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwang Kim, Seung-Beom Yoon, Kwang-Wook Koh, Chang-Hun Lee, Sung-Ho Kim, Sung-Chul Park, Ju-Ri Kim
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Patent number: 7495281Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.Type: GrantFiled: July 19, 2006Date of Patent: February 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jin Yang, Jeong-Uk Han, Kwang-Wook Koh, Jae-Hwang Kim, Sung-Chul Park, Ju-Ri Kim
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Publication number: 20090001450Abstract: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a lower semiconductor substrate, an upper semiconductor pattern on the lower semiconductor substrate, a device isolation pattern defining an active region in the lower semiconductor substrate and the upper semiconductor pattern, a lower charge storage layer between the upper semiconductor pattern and the lower semiconductor substrate, a gate conductive structure crossing over the upper semiconductor pattern, a first upper charge storage layer and a second upper charge storage layer spaced apart from each other between the gate conductive structure and the upper semiconductor pattern, and a source/drain region in the upper semiconductor pattern on both sides of the gate conductive structure.Type: ApplicationFiled: June 25, 2008Publication date: January 1, 2009Inventors: Ju-Ri Kim, Jae-Hwang Kim, Sung-Chul Park
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Publication number: 20080315289Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.Type: ApplicationFiled: August 27, 2008Publication date: December 25, 2008Inventors: JAE HWANG KIM, SEUNG-BEOM YOON, KWANG-WOOK KOH, CHANG-HUN LEE, SUNG-HO KIM, SUNG-CHUL PARK, JU-RI KIM
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Publication number: 20080316831Abstract: A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the memory cell units includes a tunnel insulation layer on the semiconductor substrate. A first memory gate and a second memory gate are disposed on the tunnel insulation layer. An isolation gate is disposed between the first and second memory gates. A word line covers the first memory gate, the second memory gate and the isolation gate. A method of forming the nonvolatile memory device is also provided.Type: ApplicationFiled: June 17, 2008Publication date: December 25, 2008Inventors: Sung-Chul Park, Jeong-Uk Han, Jae-Hwang Kim, Ju-Ri Kim
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Patent number: 7432159Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.Type: GrantFiled: October 3, 2005Date of Patent: October 7, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwang Kim, Seung-Beom Yoon, Kwang-Wook Koh, Chang-Hun Lee, Sung-Ho Kim, Sung-Chul Park, Ju-Ri Kim
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Publication number: 20080132014Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.Type: ApplicationFiled: February 4, 2008Publication date: June 5, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Weon-ho Park, Byoung-ho Kim, Hyun-khe Yoo, Seung-beom Yoon, Sung-chul Park, Ju-ri Kim, Kwang-tae Kim, Jeong-wook Han
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Patent number: 7352026Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.Type: GrantFiled: November 24, 2004Date of Patent: April 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Weon-ho Park, Byoung-ho Kim, Hyun-khe Yoo, Seung-beom Yoon, Sung-chul Park, Ju-ri Kim, Kwang-tae Kim, Jeong-wook Han
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Patent number: 7323740Abstract: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells.Type: GrantFiled: June 18, 2004Date of Patent: January 29, 2008Assignee: Samsung Electronics Co., LtdInventors: Weon-Ho Park, Sang-Soo Kim, Hyun-Khe Yoo, Sung-Chul Park, Byoung-Ho Kim, Ju-Ri Kim, Seung-Beom Yoon, Jeong-Uk Han
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Publication number: 20070298571Abstract: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells.Type: ApplicationFiled: September 4, 2007Publication date: December 27, 2007Inventors: Weon-Ho Park, Sang-Soo Kim, Hyun-Khe Yoo, Sung-Chul Park, Byoung-Ho Kim, Ju-Ri Kim, Seung-Beom Yoon, Jeong-Uk Han
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Publication number: 20070102734Abstract: Disclosed is a semiconductor device and method of fabricating the same. The semiconductor device is applicable to various electronic devices such as transistors or memories with transistors. A MOS transistor of the semiconductor device includes a first region and a second region, different in impurity concentration, which are formed in a channel region between source and drain regions. The first region is higher than the second region in impurity concentration. Impurities of the first region are concentrated on a boundary region between an active region and a field isolation film. The first region prevents a punch-through effect in the channel region, while the second region prevents current from decreasing by an increase of impurity during an operation of the transistor. The first region is formed using an additional ion implantation mask, and the second region is formed using an ion implantation mask or formed along with a well.Type: ApplicationFiled: August 4, 2006Publication date: May 10, 2007Inventors: Ju-Ri Kim, Jeong-Uk Han, Sung-Taeg Kang, Chang-Hun Lee, Sung-Chul Park
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Publication number: 20070023820Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.Type: ApplicationFiled: July 19, 2006Publication date: February 1, 2007Inventors: Seung-Jin Yang, Jeong-Uk Han, Kwang-Wook Koh, Jae-Hwang Kim, Sung-Chul Park, Ju-Ri Kim
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Publication number: 20060079045Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.Type: ApplicationFiled: October 3, 2005Publication date: April 13, 2006Inventors: Jae-Hwang Kim, Seung-Beom Yoon, Kwang-Wook Koh, Chang-Hun Lee, Sung-Ho Kim, Sung-Chul Park, Ju-Ri Kim
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Publication number: 20050117443Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure.Type: ApplicationFiled: November 24, 2004Publication date: June 2, 2005Inventors: Weon-ho Park, Byoung-ho Kim, Hyun-khe Yoo, Seung-beom Yoon, Sung-chul Park, Ju-ri Kim, Kwang-tae Kim, Jeong-wook Han
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Publication number: 20040256658Abstract: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells.Type: ApplicationFiled: June 18, 2004Publication date: December 23, 2004Inventors: Weon-Ho Park, Sang-Soo Kim, Hyun-Khe Yoo, Sung-Chul Park, Byoung-Ho Kim, Ju-Ri Kim, Seung-Beom Yoon, Jeong-Uk Han