Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: A method of beam administration in a cellular or wireless network is proposed. Cellular/wireless networks operating at Ka or higher frequency band require the use of directional antenna (or through array-based beamforming) to compensate for sever pathloss. Maintaining antenna pointing and tracking accuracy is essential in many phases of the communication process. By using uplink pilot signals for beam alignment/tracking, combined with switched beamforming at the UE and adaptive beamforming at the BS, an effective beam administration is achieved with reduced overhead, complexity, and cost.

Abstract: Aspects of the disclosure provide an apparatus that includes a transceiver circuit and a baseband processing circuit. The transceiver circuit is configured to transmit signals that carry a data unit to another apparatus and receive signals that carry a response from the other apparatus. The baseband processing circuit is configured to provide a first digital stream to carry a data unit to the transceiver circuit for transmission, and provide a second digital stream to carry a portion of the data unit to the transceiver circuit for retransmission when the transceiver circuit receives a response that is indicative of a partial receiving failure of the data unit at the other apparatus.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

Abstract: Techniques and examples pertaining to codeword mapping in New Radio (NR) and interleaver design for NR are described. A processor of an apparatus receives, via a transceiver of the apparatus, a Physical Downlink Shared Channel (PDSCH) transmission from a network node of a wireless network. The processor maps one or more codeblocks of a codeword in the PDSCH transmission to a spatial layer group which is a subset of a plurality of spatial layers. The processor also performs receive processing for one or more codeblocks in the PDSCH transmission including by performing de-interleaving on a result from a channel interleaver or from an intra-codeblock interleaver that performs pseudo-random interleaving on systematic bits and parity bits of the one or more codeblocks and channel decoding. The processor transmits, via the transceiver, to the network node a feedback concerning the one or more codeblock and reporting a result of the channel estimation.

Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.

Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.

Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.

Abstract: Apparatus and methods are provided for RE allocation for UCI on PUSCH. In one novel aspect, the UE encodes UCI for transmission on PUSCH in a NR network. The UE allocates UCI REs onto the PUSCH following one or more UCI RE allocation rules including (a) using same logical allocation patterns for both CP-OFDM waveforms and DFT-S-OFDM waveforms, (b) distributing the UCI REs across a time domain of the PUSCH, and (c) distributing the UCI REs across a frequency domain for CP-OFDM or across a virtual-time domain for DFT-S-OFDM. In one embodiment, the HARQ-ACK REs are distributed across the time domain as much as possible. In another embodiment, the allocation of the HARQ-ACK REs further involves calculating the number of HARQ REs dynamically for the HARQ ACK. The number of HARQ REs is based on a weighting parameter, which is either configured or obtained through system information.

Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.

Abstract: A system for acquiring channel knowledge and a method thereof are provided. At least one transmitter generates multiple directional beams in different directions, next modulates the directional beams in the different directions with at least one spreading sequence, so as to enlarge the beam range of each directional beam in the different directions and use the modulated directional beams as training-specific beams in the different directions, and sweeps the multiple training-specific beams in the different directions by using a plurality of antennas, so that at least one receiver measures at least one training-specific beam, and determines the channel knowledge according to the measurement result and beam-related information associated with the at least one training-specific beam, so as to achieve a technical effect of reducing training overhead.

Abstract: A Hybrid Automatic Repeat Request (HARQ) feedback scheme that employs a multi-state NACK feedback processing is proposed. A transport block (TB) contains a plurality of code blocks (CBs). When all CBs of the TB are successfully decoded, a one-bit TB ACK is feedback. When at least one CB of the TB is not correctly decoded, a one-bit TB NACK is feedback. In addition, a multi-bit HARQ CB NACK feedback is provided. The multi-bit HARQ CB NACK can point more precisely to the erroneous parts of the TB and trigger efficient retransmission by skipping retransmission of successfully decoded CBs. The network can disable the multi-bit CB NACK for certain UEs, e.g., to reduce overhead. The UE can disable the multi-bit CB NACK, e.g., to save power.