Patents by Inventor Ju-Ya Luo

Ju-Ya Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8749214
    Abstract: A power circuit includes a control unit, a logic control circuit, a first driver amplifier, a second driver amplifier and a logic determination circuit. The control unit is used to output a pulse width modulation (PWM) signal and an enable (EN) signal. The logic control circuit receives the PWM signal and the EN signal, and outputs a first voltage signal and a second voltage signal. The first driver amplifier receives the first voltage signal, and outputs a first gate (UGATE) drive signal. The second driver amplifier receives the second voltage signal, and outputs a second gate (LGATE) drive signal. The logic determination circuit receives the PWM signal and the first and second gate drive signals. When the PWM signal and the first and second gate drive signals meet an abnormal logical relation, the logic determination circuit disables the logic control circuit.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Asus Technology Pte Ltd
    Inventors: Bing-Bing Xu, Ju-Ya Luo, Zhao-Long Dong, Ching-Ji Liang
  • Publication number: 20120146600
    Abstract: A power circuit includes a control unit, a logic control circuit, a first driver amplifier, a second driver amplifier and a logic determination circuit. The control unit is used to output a pulse width modulation (PWM) signal and an enable (EN) signal. The logic control circuit receives the PWM signal and the EN signal, and outputs a first voltage signal and a second voltage signal. The first driver amplifier receives the first voltage signal, and outputs a first gate (UGATE) drive signal. The second driver amplifier receives the second voltage signal, and outputs a second gate (LGATE) drive signal. The logic determination circuit receives the PWM signal and the first and second gate drive signals. When the PWM signal and the first and second gate drive signals meet an abnormal logical relation, the logic determination circuit disables the logic control circuit.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 14, 2012
    Inventors: Bing-Bing XU, Ju-Ya LUO, Zhao-Long DONG, Ching-Ji LIANG
  • Publication number: 20110007434
    Abstract: The invention discloses an over current protecting device and the method thereof. The over current protecting device is adapted to a DC-DC converter. A voltage output end of the DC-DC converter may generate an output current and transmit the output current to a load on a motherboard via a power copper layer on the motherboard. The over current protecting method includes the following steps: detecting a voltage drop on the power copper layer; controlling the DC-DC converter to operate normally when the voltage drop is smaller than a threshold value; and controlling the DC-DC converter to stop operating when the voltage drop is larger than the threshold value.
    Type: Application
    Filed: July 6, 2010
    Publication date: January 13, 2011
    Applicants: ASUS TECHNOLOGY (SUZHOU) CO. LTD, ASUSTEK COMPUTER INC.
    Inventors: Wei Han, Ching-Ji Liang, Chai-Lin Yu, Ju-Ya Luo