Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: A memory connector with an increased pin interval is disclosed including a main body and a plurality of pins. The body includes a bottom, and the pins are disposed on the bottom along a longitudinal direction in an interlaced way. A recess is formed on the bottom of the main body corresponding to each of the pins at one end of the pin. The arrangement of the pins therein solves the problem of insufficient space for wiring lines of the main board, which is occurred frequently when the pins are fabricated by an SMD process, without increasing any manufacturing cost in particular.

Abstract: In a pulse width modulation (PWM) control device and driving method, the PWM control device includes a PWM device, for providing a plurality of PWM signals; and a controller electrically connected to the PWM device and a plurality of driving circuits, for controlling PWM signals to arbitrarily enable or disable the plurality of driving circuits according to load capacity; wherein when driving circuits are damaged, the controller disables the damaged driving circuits and replaces the damaged driving circuits with the other driving circuits.

Abstract: A flash memory control device includes a controller and an expansion device. The expansion device is electrically connected to the controller and one and more flash memory devices for temporarily storing data, integrating data and presenting processing status, wherein the controller orders the expansion device to transform data to the one and more flash memory devices or receive data from the one and more flash memory devices according to processing status.

Abstract: A data transmission device and a method for the same are proposed. The data transmission device has a first storage device, a second storage device and a transmission control unit controlling the data transfer between a chip set, the first storage device and the second storage device. When the data transfer is performed, the transmission control device checks whether a destination device completely receives the data sent. If positive, the destination device receives the data immediately. Otherwise, a portion of the data is first sent to the destination device and a remaining portion is temporarily stored in the second storage device. Thus, using the transmission control unit improves the transmission efficiency. Furthermore, via storing booting data in the second storage device and using a PCI-Express (PCI-E) interface for data transfer, booting a computer by accessing the data of the second storage device reduces the booting time.

Abstract: An interface system of a serial advanced technology attachment (SATA) having speedy data access function and method thereof, wherein the memory in the system may be expanded by the user, which is used as the buffer or cache between the SATA device and the south-bridge chip. The data storage destination is determined according to the degree of occupancy of the control module, as such achieving the purpose and effectiveness of increasing the speed of data access.

Abstract: A data transmission device and a method for the same are proposed. The data transmission device has a first storage device, a second storage device and a transmission control unit controlling the data transfer between a chip set, the first storage device and the second storage device. When the data transfer is performed, the transmission control device checks whether a destination device completely receives the data sent. If positive, the destination device receives the data immediately. Otherwise, a portion of the data is first sent to the destination device and a remaining portion is temporarily stored in the second storage device. Thus, using the transmission control unit improves the transmission efficiency. Furthermore, via storing booting data in the second storage device and using a PCI-Express (PCI-E) interface for data transfer, booting a computer by accessing the data of the second storage device reduces the booting time.

Abstract: A display apparatus for a multi-display card and displaying method of the same is disclosed. The display apparatus for a multi-display card comprises: a first chipset with a first socket, a second chipset with a second socket, a first display card, a second display card, and a connector. The first display card is inserted into the first socket and the second display card is inserted into the second socket, and the connector is connected between the first display card and the second display card. The first display card and the second display card are controlled separately through the first chipset and the second chipset for handling image processing, and the first display card and the second display card are co-operated through the connector to output a video signal. Thereby, it increases the efficiency of the image processing.

Abstract: An operating method is disclosed for dynamic physical network layer monitoring. A plurality of built-in or extended network interface cards in a computer are to be merged or separated for multitasking operation, redundancy or any emergent application through continuously monitoring the network status. The network devices connected with the computer are checked after switching the computer on in the first step. Next, the drivers thereof are loaded to activate and initialize the network devices, and the connection therebetween is established. Afterward, the method further includes determining whether the devices need to be re-activated by continuously monitoring the network status.

Abstract: A method and device for detecting a current are described. The present invention displays a value and looks for loads current of the CPU through an LED, a 7-segment display or a display monitor.