Patents by Inventor Ju-Yuan Hsiao

Ju-Yuan Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120091816
    Abstract: In one embodiment, a power system includes a first power source having a first voltage, a second power source having a second voltage, and a controller. The controller is coupled to the first power source and the second power source. The controller compares the first voltage with the second voltage, controls the first power source to charge the second power source via a first switch and a second switch in a charging mode when the first voltage is greater than said second voltage, and controls the second power source to power a load such as a light-emitting diode (LED) light source via the second switch and a third switch in a load-powering mode when the second voltage is greater than the first voltage.
    Type: Application
    Filed: November 4, 2011
    Publication date: April 19, 2012
    Applicant: O2MICRO, INC.
    Inventors: Da LIU, Sheng-Tai LEE, Ju-Yuan HSIAO, Chang-Yi LIN
  • Patent number: 7639801
    Abstract: A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial: P ? ( x ) = ? q = 0 N ? c q ? x q ? ? or ? ? b ? ( i ) = ? q = 1 N ? c q ? b ? ( i - q ) . The method first determines a transformation formula: b ? ( kN + i ) = ? q = 1 N ? c q ? b ? ( ( k - R ) ? N + i + R ? ( N - q ) ) according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M?2, bMj+M?1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: December 29, 2009
    Assignee: National Central University
    Inventors: Shyh-Jye Jou, Chih-Ning Chen, You-Jiun Wang, Ju-Yuan Hsiao, Chih-Hsien Lin
  • Publication number: 20060029225
    Abstract: A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial: P ? ( x ) = ? q = 0 N ? c q ? x q ? ? ? or ? ? ? b ? ( i ) = ? q = 1 N ? c q ? b ? ( i - q ) . The method first determines a transformation formula: b ? ( kN + i ) = ? q = 1 N ? c q ? b ? ( ( k - R ) ? N + i + R ? ( N - q ) ) according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M?2, bMj+M?1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula.
    Type: Application
    Filed: March 31, 2005
    Publication date: February 9, 2006
    Inventors: Shyh-Jye Jou, Chih-Ning Chen, You-Jiun Wang, Ju-Yuan Hsiao, Chih-Hsien Lin