Patents by Inventor Ju-Yuan TZENG

Ju-Yuan TZENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230268404
    Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: Ming-Chia Tai, Ju-Yuan Tzeng, Hsin-Che Chiang, Yuan-Sheng Huang, Chun-Sheng Liang
  • Publication number: 20230268406
    Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 24, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH
  • Patent number: 11670695
    Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chia Tai, Ju-Yuan Tzeng, Hsin-Che Chiang, Yuan-Sheng Huang, Chun-Sheng Liang
  • Patent number: 11670697
    Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Chih-Yang Yeh, Shu-Hui Wang, Jeng-Ya David Yeh
  • Patent number: 11295990
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 11145730
    Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-Ya David Yeh
  • Publication number: 20210313437
    Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH
  • Publication number: 20210234013
    Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: Ming-Chia Tai, Ju-Yuan Tzeng, Hsin-Che Chiang, Yuan-Sheng Huang, Chun-Sheng Liang
  • Patent number: 11043567
    Abstract: A semiconductor device includes a substrate, a gate stack. The substrate includes a semiconductor fin. The gate stack is disposed on the semiconductor fin. The gate stack includes a dielectric layer disposed over the semiconductor fin, and a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, and a gate electrode disposed over the metal stack. The first metallic layer and the second metallic layer have a first element, and a percentage of the first element in the first metallic layer is greater than that in the second metallic layer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Chih-Yang Yeh, Shu-Hui Wang, Jeng-Ya David Yeh
  • Patent number: 10991805
    Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chia Tai, Ju-Yuan Tzeng, Hsin-Che Chiang, Yuan-Sheng Huang, Chun-Sheng Liang
  • Patent number: 10867806
    Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Kuo-Hua Pan
  • Publication number: 20200152521
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20200075741
    Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Chih-Yang YEH, Jeng-Ya David YEH
  • Publication number: 20200044037
    Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: Ming-Chia Tai, Ju-Yuan Tzeng, Hsin-Che Chiang, Yuan-Sheng Huang, Chun-Sheng Liang
  • Patent number: 10529629
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20190393326
    Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 26, 2019
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Kuo-Hua PAN
  • Patent number: 10475895
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-ya David Yeh
  • Publication number: 20190333826
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 10403737
    Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: September 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Kuo-Hua Pan
  • Publication number: 20190165117
    Abstract: A semiconductor device includes a substrate, a gate stack. The substrate includes a semiconductor fin. The gate stack is disposed on the semiconductor fin. The gate stack includes a dielectric layer disposed over the semiconductor fin, and a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, and a gate electrode disposed over the metal stack. The first metallic layer and the second metallic layer have a first element, and a percentage of the first element in the first metallic layer is greater than that in the second metallic layer.
    Type: Application
    Filed: August 28, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH